SPI Clock Signal Configuration

[JonConesa]

Hi everyone,

I’m encountering problems with SPI communication with the board NUCLEO-H753ZI and the EVAL-AD5764 from Analog Devices, as this is my first time working with it, and I’m unsure if I’ve configured it correctly.

I’ve consulted a forum for Analog Devices, and they pointed out that I’m incorrectly generating the CLK signal.

Specifically, I’m trying to transmit a 24-bit signal, aiming for 24 rising edges and 24 falling edges of the CLK signal while the CS line is low. However, when I use HAL_SPI_Transmit, I observe 24 rising edges and only 23 falling edges during the CS low period. The final falling edge occurs approximately 100 μs after the CS line goes high.

After some testing, I modified the clock phase to “2nd Edge,” which successfully generates the CLK signal as I wanted. However, now it’s no longer writing the expected data to the slave device.

I’ve attached the following for reference:

• The code I’m using

HAL_StatusTypeDef ret;
 int32_t wr_ret = (int32_t)EMBL_WRONGPARAMS;
 SPI_HandleTypeDef *hPDev = (SPI_HandleTypeDef *)WRSPI_getPhysicalDevice(hSPI);

 if (hPDev != NULL && pData != NULL && DataSize > 0){
 WRSPI_setCSS(hSPI, false);
 do {
 ret = HAL_SPI_Transmit(hPDev, pData, DataSize, 1000);
 } while (ret == HAL_BUSY);
 if (ret != HAL_OK){
 wr_ret = EMBL_ERROR;
 }else {
 wr_ret = EMBL_OK;
 }
 WRSPI_setCSS(hSPI, true);
 }

• A capture from the logic analyzer with the clock phase to “1nd Edge,”

• A capture from the logic analyzer with the clock phase to “2nd Edge,”

• My CubeMX configuration

 

I’d appreciate any guidance on what might be causing these issues or how to resolve them.

Thank you in advance!

[JBias]

Hi Jon,

Looks like you got the correct configuration with the 2-line SPI parameter. 

Are the MOSI and MISO lines reversed? The output data you are writing should be on the MOSI (Master Out Slave In) signal.

I would check that pData is what you want it to be. For a test you can even hard code it.

Good luck

[JonConesa]

Hi JBias,

The MOSI and MISO signals are correctly generated. I just checked, and the labels in the logic analyzer were swapped.

However, I think the issue is with the CLK signal. After CS goes high again, the CLK remains high for 70 µs after the last clock pulse. Is this expected behavior? Is the CLK signal being generated correctly?

Best,

Jon

[AScha.3]

Hi,

>the CLK remains high for 70 µs after the last clock pulse. Is this expected behavior?

you can set the interface, to keep the state:

>Is the CLK signal being generated correctly?

probably yes - as you set it. So change setting, if you want it to behave in an other way.

[MasterT]

Seems like Errata, ES0392 - Rev 13 - September 2024:

2.22.6 Truncation of SPI output signals after EOT event
Description
After an EOT event signaling the end of a non-zero transfer size transaction (TSIZE > 0) upon sampling the last
data bit, the software may disable the SPI peripheral. As expected, disabling SPI deactivates the SPI outputs
(SCK, MOSI and SS when the SPI operates as a master, MISO when as a slave), by making them float or
statically output their by-default levels, according to the AFCNTR bit of the SPI_CFG2 register.
With fast software execution (high PCLK frequency) and slow SPI (low SCK frequency), the SPI disable occurring
too fast may result in truncating the SPI output signals. For example, the device operating as a master then
generates an asymmetric last SCK pulse (with CPHA = 0), which may prevent the correct last data bit reception
by the other node involved in the communication.
Workaround
Apply one of the following measures or their combination:
• Add a delay between the EOT event and SPI disable action.
• Decrease the ratio between PCLK and SCK frequencies.