SPI communication between two STM3 boards

[Pluto7]

Hi All,

Hope you are doing well.

I am working on SPI communication between two STM32 boards (F7 as master and WB55 as slave), but I am encountering issues with reliable data transfer.

The problem arises with the transfer of 2-byte data packets. Initially, the data is transmitted successfully for a certain number of iterations, but after that, the received data becomes corrupted. Additionally, there are instances where the received data is incorrect from the very beginning of the communication.

I am using the example SPI communication code provided by STM32, with one board configured as master and the other as slave.

Has anyone experienced similar issues or can provide insights on how to ensure more reliable data transfer between the boards?

MY SPI Settings:

Parameters	Master	Slave
Data Size	8 bits	8 bits
First Bit	MSB  First	MSB  First
CPOL	Low	Low
CPHA	1 Edge	1 Edge
MOSI	Pull Down	Pull Down
MISO	Pull Down	No pull up and No pull down
SCK	Pull Down	No pull up and No pull down

Any help or tips on this will be helpful.

Thanks & regards,
Pluto

[AScha.3]

Hi,

>Has anyone experienced similar issues 

Well, what is the "issue" then ? (You dont show any right -> wrong values... so just guessing)

How long is the connection cpu - cpu ? speed ? screened ? NSS ?

Because there is a basic problem: if you just let it run , with 8 clks -> 1 byte transmitted, in endless loop : 

what if there any short spike on the clk line ? It will shift one bit random in and you never get a correct byte in receiver again...except you have some way, to re-sync the transmission. Or be sure, there can be no EMI/spike, because screened and only 30mm distance (example), but even then: how to be sure its correct received after power down and starting of one of the cpus ?

So:

- you look for SPI error flags ? and handle them...

- you have NSS (hardware), to get a "frame" info

- you have a control byte or CRC in your transmission protocol ?

- you have thought about a way to "resync" in case of wrong control byte or CRC ? -> (disable/restart SPI unit)

 

[David Littell]

You've given us basically nothing to work with.

Code?  (Don't forget the code tags!)  DMA used on either end?  Connection length & SCLK speed?  Data cache(s) enabled?  Do you have a scope or logic analyzer?

[farioez]

I have the same problem . I was trying to send serial 16 bits data from Master that is written on HAL and slave one is written on register level using SPI RX IRQ. My aim is to send serial three channel data via 16 bits from the array at Master side, so that they can be processed to be distributed over three channel buffers at the reception side . But the main purpose of using three channels is sending other devices for simulatenous data transmission/reception  on DMA-SPI channels to  . I somehow adjusted the speed max (in my case 50 MHz) so that I can get the more appropriate data, but still after some clock cycle the data gets corrupted. I checked data at the cable between master-to-slave on osci, the data were sent correctly. At the reception side, corruption of data starts to appear. In my opinion, it relates to speed of the SPI or GPIO. But still I have tried different variations of speed, number of bits (8,16,32), MSB/LSB, Software/Hardware CS,  DMA/Not DMA. These did not work at all.

[farioez]

I found the solution by fixing these;

1. Personal mistakes on code of SPI interrupt while extracting the data.

2. SPI Cable problem : I replaced the new one . Then it worked.

3. I made the speed again 3,125 MHz which provides the decent data flow for my case.