SPI communication failure at high frequicies

[pozeetive]

Hi, 

The SPI communication between an ESP(Master) and the STM(Slave) is failing when i configure the SPI clock at 10MHz.

I have STM32F429ZIT6 DISC1 board and i have used SPI3 as slave, the SPI3 is on the APB1 bus which is configured at 45MHz PCLK.

The communication is well and good at 8MHz SPI_CLK but when i configure it at 10MHz SPI_CLK it is failing, the control is stuck at : 

	 if(HAL_SPI_Receive(&hspi3, buf, sizeof(buf), 0xffff) != HAL_OK){
		 Error_Handler();
	 }

 

I'm unable to find out what may be the issue, as the slave's PCLK is 2xSPI_CLK, it should work right?

[Petr Sladecek]

Hello,

it is not quite clear what is neither bus wide (1/2 data lines? any extreme bus length/load is excluded?), nor configured SPI mode (full duplex, simplex, bidi, HW/SW NSS control, data size, FIFO threshold vs number of data ..), nor HAL drivers version, nor information about the observed error (wrong number of data? wrong data received? any SPI error is raised e.g. OVR, CRC?). Only information is "polling mode applied upon SPI3 slave". If slave is simplex receiver, while suppose all the data are provided correctly on the bus by the master, the only risk is that polling is not managed by the SW in time or correct data packing control is missed at case the number of data is not aligned with the FIFO threshold. I suggest to study AN5543 focused on the problematic aspects of communication at this older version of the SPI design especially or provide us more complex information to better understand what can go wrong.

Best regards,

Petr