SPi communication in stm32f407vgtx board

[Ash1]

Hi all

I am working with SPI1 on stm32f407vgtx and issue what I am, facing my NSS which internally controlled by SPI is taking more time for goes high even CLOCk has been stopped . my configuration are SPI full duplex 16 bit data clock is 2.6MHZ after prescaled I am transmitting on spi every 10ms task. Please check the screenshot of logic analyzer for further understanding .

Note: in the end I have disabled SPE bit  before checking TXE and busy flags.

 

 

[TDK]

NSS remaining low is not a problem for the SPI protocol. On the STM32F4, NSS will remain low as long as the SPI peripheral is enabled. I recommend using a GPIO pin for the CS pin.

[Ash1]

Hi

I have a observed that every times after 4th CLOCK 5th clock is taking twice than rest.

why it happening please check the image.

 

[TDK]

This is a sampling rate issue. Increase the sampling rate on the logic analyzer and/or slow down the SPI clock speed if this bothers you.

[Ash1]

Hi

I am waiting for your response .

B.R

Ash

[TDK]

> HAL_SPI_Transmit(&hspi1, TX_Buffer, 1, 1000);

This is the only SPI-related statement in your code. I don't see manipulation of CS anywhere or disabling the SPI peripheral anywhere.

Still stand by my first statement. NSS will be low as long as the peripheral is enabled. Better to use a GPIO pin here.

[Andrew Neil]

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@TDK wrote:

Still stand by my first statement. NSS will be low as long as the peripheral is enabled. .

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Indeed - that is the defined behaviour:

https://www.st.com/resource/en/reference_manual/rm0090-stm32f405415-stm32f407417-stm32f427437-and-stm32f429439-advanced-armbased-32bit-mcus-stmicroelectronics.pdf#page=880

via: https://www.st.com/en/microcontrollers-microprocessors/stm32f407vg.html#documentation

 

[Ash1]

Duplicate - merged.

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Hi all

The slave device I intend to use needs to use requires CS to toggle with each SPI Command [16 bit length]. The Requirement is to use Peripheral controlled CS hence I cannot use GPIO.

During Transmission we are able to observe the Data correctly over MOSI. Currently Default 0xFF on MISO as Slave is not connected.

The issue we see is additional ~1.5 us is taken by SPI controlled CS to go to High after Clock stops.To make CS high SPI is disabled via bit SPE =0 in CR1 after TXE = 1 and BSY= 0

• Is this intended behavior??
• Why additional time needed and what is the functionality executed in this period?
• Is there any default Setup Delay or Hold Delay implemented as SCI Clocks stops 1.4us before the SCI is High?

Note : Please check once the image that I have shared.

B.R

Ash

[waclawek.jan]

The SPI hardware does not set NSS (CS) high actively.

If you use Cube/HAL, it probably disables SPI entirely (by clearing SPIx_CR.SPE) after transmission. This threestates the SPI pins, i.e. does not pull them up actively, although you mayu have enabled internal pullups on the NSS (CS) and SCK pins.

You can try to set the NSS (CS) pin to GPIO output and control it in software to generate the required framing, but again if you rely on Cube/HAL, the software overhead of it may prevent you to act quickly enough.

JW