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Visitor II
December 10, 2022
Question

Stack in SRAM2 on STM32F413VGT6

  • December 10, 2022
  • 2 replies
  • 1317 views

Hi guys,

I need your collective intelligence, because I am a bit lost on the information given by the ST datasheets and reference manuals.

Backstory: on a few of our prototypes we started to see random failing behavior and investigated quite a bit. The faulty behavior seems to start when the stack lies in SRAM2 region. KEILs default linker file has IROM region from 0x20000000 to 0x20005000 which is SRAM1 and SRAM2 together as one region.

Could it indeed be that the Stack in SRAM2 or even over the edge between SRAM1 and SRAM2 could cause faulty behavior? Or is this a dead end?

Best Regards,

Patrick

    This topic has been closed for replies.

    2 replies

    Super User
    December 10, 2022

    > The faulty behavior seems to start when the stack lies in SRAM2 region.

    Which address, 0x1000xxxx or 0x2004xxxx?

    In any case, stack location is unlikely to cause any problems directly, read, it's probably a program error, maybe masked with e.g. somewhat slower execution if processor accessing stack collides with other bus masters such as DMA.

    JW

    Visitor II
    December 10, 2022

    Hi and thanks for your answer!

    I am using RAM from 0x20000000 to 0x20050000 so 0x2004xxxx.

    When I increase the HEAP size and therefore push the Stack deeper down into SRAM2 the errors start to occur.

    As I cannot debug the error because when stepping it does not occur this indeed sounds like program execution time error?

    Do you have any advice in debugging/hunting down the error?

    Super User
    March 16, 2024

    Hi @patrickschneider9 ,

    I wonder, if you've had luck with resolving this issue.

    Thanks,

    JW

    Technical Moderator
    March 16, 2024

    Hi @waclawek.jan ,

    Thank you for reaching back this Open Thread . It is quite interesting to know the root cause or how to reproduce that faulty behavior ( it seems not on all devices ) so may be due to Timings conflict with Cortex-M4 ? To be debugged . SRAM2 is 64Kbytes is mainly used for have critical Code routine to run with I-code , but is contiguous with SRAM1 so may be there is a multiple Load transaction crossing them . 

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    @patrickschneider9  Your feedback is much appreciated ! 
    Ciao

    STOne-32