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Visitor II
June 11, 2025
Solved

STM32 H757 FMC Controller stall after couple of reads on M7 core

  • June 11, 2025
  • 1 reply
  • 301 views

Hi all,

currently iam using the stm32h757 controller.

i want to use the FMC on both cores, in SRAM mode with this config:

 hsram1.Instance = FMC_NORSRAM_DEVICE;
 hsram1.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
 /* hsram1.Init */
 hsram1.Init.NSBank = FMC_NORSRAM_BANK1;
 hsram1.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
 hsram1.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
 hsram1.Init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
 hsram1.Init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
 hsram1.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
 hsram1.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
 hsram1.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
 hsram1.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
 hsram1.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
 hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
 hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
 hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
 hsram1.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
 hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
 /* Timing */
 Timing.AddressSetupTime = 2;
 Timing.AddressHoldTime = 2;
 Timing.DataSetupTime = 3;
 Timing.BusTurnAroundDuration = 2;
 Timing.CLKDivision = 16;
 Timing.DataLatency = 17;
 Timing.AccessMode = FMC_ACCESS_MODE_A;


When i read the FMC address from the M4 core multiple times, i have no problem and can read data. For example like this:

tmp_data = *((__IO uint16_t *) 0x60014a72);


But when i read from the M7 core, i can read like 1-2 times, and then i won't receive any data anymore.


On the Oscilloscope i can see that the NE & NOE Pins will not be reset and stay high after the second read (for the successful reads, the NE & NOE are reset as expected).

What i did so far:
- Aligned all address to be even (as suggested in the errata sheet ES0445 - Rev 5)
- created two minimal examples where only one core M4 (respectively the M7) is initializing and using the FMC. So no interaction from the other core can interfere.

 

Is this a known issue/behavior, or did someone experience the same ?

 

Best regards

    This topic has been closed for replies.
    Best answer by Pat_btmn

    I manage to solve the problem.

    It is very similar to this post:

    https://community.st.com/t5/stm32-mcus-products/known-issues-with-d-cache-and-fmc-on-stm32f7/td-p/276025

    Like in the post, I saw the same behavior for the NOE on the Oscilloscope. As written, disabling the D-Cache solved the problem!

    I will exclude the FMC address from caching, as suggested.

    1 reply

    Pat_btmnAuthorAnswer
    Visitor II
    June 12, 2025

    I manage to solve the problem.

    It is very similar to this post:

    https://community.st.com/t5/stm32-mcus-products/known-issues-with-d-cache-and-fmc-on-stm32f7/td-p/276025

    Like in the post, I saw the same behavior for the NOE on the Oscilloscope. As written, disabling the D-Cache solved the problem!

    I will exclude the FMC address from caching, as suggested.