STM32 SPI receive always shifted 3-4 bytes

[volker2]

Posted on January 15, 2017 at 18:50

Hallo,  i use the HAL to program a little test software to transfer data via spi between

two STM32 Nucleo boards.

One board with a STM32L476 sends every 5 ms 74 bytes of data as a spi master with 625 kBit.

Chip select is used as GPIO output. clock is high if idle, CS is low active,

data valid with faling edge of clock.

A secon Nucleo64 should receive this 74 byte, configured as spi slave without NSS usage.

CS is used as an IRQ input with detection of the faling edge. DMA on den and receive, in normal mode.

I have programmed, that with the falling edge IRQ of the CS, the function

HAL_SPI_TransmitReceive_DMA() will be called. On the first NUCLEO i can adjust a time, so

that CS will be low a short time before the data was sent (I tried 50µs).The slave receives data, but the data was shifted. So the first 3 or 4 bytes in my

receive-array will be the last 3-4 bytes of the telegram before. And then the new data was

in the array.

I don't understand that behaviour. Controlled with the logic analyser everything is correct.

Do you know a solution for that?

Best regards

Volker

[arturro]

I have the same problem. As a solution, I tried to use EXTI interrupt for SS line. Inside the EXTI handler, I call HAL_SPI_Abort just before HAL_SPI_Receive_DMA. Sometimes it helps, but not always.

[PJano.1]

same issues...

[Nikolaj_TL]

I have the same issue on the SPI Slave RxBuffer. It is offset by 4-bytes.

Has anybody resolved the issue?

[David Littell]

Yes but a general-case solution requires much more sophisticated synchronization between the SPI Master and Slave than just "Master-asserts-NSS-and-waits-a-while-before-sending".