Skip to main content
Super User
September 5, 2024
Solved

STM32F030 PC13,14,15 current sink limits?

  • September 5, 2024
  • 4 replies
  • 2383 views

AndrewNeil_0-1725556635883.png

 

Is it OK to use these pins as current sinks for driving LEDs ?

 

AndrewNeil_1-1725557015423.png

 

    This topic has been closed for replies.
    Best answer by STTwo-32

    Hello @Andrew Neil @Tesla DeLorean @AScha.3 

    Sorry for my late replay, I just received this answer from the concerned person:

    " The switch is only impacting GPIO source capabilities. No limitations if IO is set in output low level."

    Best Regards.

    STTwo-32

    4 replies

    Technical Moderator
    September 5, 2024

    Hello @Andrew Neil 

    As it is mentionned on the 3rd line of the note on the screenshot:

    "These GPIOs must not be used as current sources (e.g. to drive an LED)." For Curent sink, i will check this and get back to you ASAP.

    Best Regards.

    STTwo-32 

    Graduate II
    September 5, 2024

    Good question, the P/N gates probably the same size, but the ground ring is probably more robust, and not gated like VDD/VBAT path

    I'd tend toward it being Ok, but will watch for the official response.

    Slack pins for LEDs, the PA13/PA14 often can be used and still facilitate debug connectivity if the code is aware.

    Super User
    September 5, 2024

    plus the reason stated for the limitation is that these pins are fed  "through the power switch", and that's what limits their sourcing capabilities.

    I presume this is "the power switch":

    AndrewNeil_0-1725559013974.png

     

    On that basis, if it's the whole story, sinking should be OK ... ?

     

    "the switch only sinks (sic?) a limited amount of current" sounds like a typo, though?

     

    Graduate II
    September 5, 2024

    >>plus the reason stated for the limitation is that these pins are fed "through the power switch", and that's what limits their sourcing capabilities.

    What's gating it, or how robust the wiring/metalization is feeding it across the die.

    That was definitely my "hot-take" on the documentations wording, and that the return-path on the common VSS side was significantly more substantial, and not switched/gated.

    The geometry of the IOCELL's transistor might also be smaller/slower, I vaguely recall a +/- 3mA specification in some STM32 family docs.

    STTwo-32Answer
    Technical Moderator
    September 17, 2024

    Hello @Andrew Neil @Tesla DeLorean @AScha.3 

    Sorry for my late replay, I just received this answer from the concerned person:

    " The switch is only impacting GPIO source capabilities. No limitations if IO is set in output low level."

    Best Regards.

    STTwo-32

    Super User
    September 17, 2024

    Thanks - it would be helpful if that could be clarified in the datasheet.

    Super User
    September 17, 2024

    @Tesla DeLorean,

    Nice pun! :)

    @Andrew Neil,

    Great question too!

    @STTwo-32,

    > Thanks - it would be helpful if that could be clarified in the datasheet.

    +1  (and I'd spell it "datasheets").

    JW

     

    Super User
    February 12, 2025