STM32F103 - Confusing statement in DMA req mapping section 13.3.7, page 281 of RM0008
Being fairly new to the STM32 architecture I find the following statement in the STM32F103 reference manual really confusing ...
"..., this means that only one request must be enabled at a time."
(the same also applies to the DMA2 controller).
I think this statement should read as follows....
"..., this means that only one request can be serviced at a time."
From my understanding (correct me if I am wrong) each DMA channel has its own interrupt vector (and their own addr\counter registers) , so even if every channel on DMA1 was enabled & signaled a request simultaneously the processor would be able to service each request deterministically based on the built-in channel priority order.
