STM32F103 FSMC - Usage Of Both NOR Flash (on NE1) and SRAM (on NE2)

[selaslan1]

Hi

We have designed a board that we used STM32F103ZGT6.

We have used FSMC with following specifications

- On NE1 - NOR FLASH (M29W640GT)

- On NE2 - SRAM (Renesas RMLV1616 series)

Everything is clear and normal for SRAM. We can read&write successfully.

But We could not access to flash memory.

We have tested 5 different board

What is wrong?

Is there any problem to use both SRAM and NOR flash in same project?

 

 

 

 

[waclawek.jan]

> We could not access to flash memory.

What are the connections? What did you do in software? What was the expected behaviour and what was the observed one? 

JW

[selaslan1]

Actually the connections are same as STM32-EVAL (STM32F103ZE)
We have just forgotten to use pull up resistor for CE (NEx) pins with 10K resistor

In our current design

NE1 for NOR Flash

NE2 for SRAM

As I said you before everything is ok for SRAM

Regarding NOR Flash

Here is the code for initialization. I have changed some values for timing. But no more change.

Sometimes We read FF values for the bytes. But could not program flash.

Sometimes We read random values from Flash

Sometimes The code is waiting in undefined state.

 

void FSMC_NOR_Init(void)
{
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
FSMC_NORSRAMTimingInitTypeDef p;
GPIO_InitTypeDef GPIO_InitStructure;

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE |
RCC_APB2Periph_GPIOF | RCC_APB2Periph_GPIOG, ENABLE);

/*-- GPIO Configuration ------------------------------------------------------*/
/* NOR Data lines configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 |
GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
GPIO_Pin_15;
GPIO_Init(GPIOE, &GPIO_InitStructure);

/* NOR Address lines configuration */
// A0-A1-A2-A3-A4-A5-A6-A7-A8-A9
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
GPIO_Pin_14 | GPIO_Pin_15;
GPIO_Init(GPIOF, &GPIO_InitStructure);

// A10-A11-A12-A13-A14-A15
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 |
GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOG, &GPIO_InitStructure);

// A16-A17-A18
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
GPIO_Init(GPIOD, &GPIO_InitStructure);

// A19-A20-A21;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOE, &GPIO_InitStructure);

// NOE, NWE configuration
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
GPIO_Init(GPIOD, &GPIO_InitStructure);

// NE1 (Flash) configuration
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
GPIO_Init(GPIOD, &GPIO_InitStructure);

// // NWAIT (Flash) configuration
// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
// GPIO_Init(GPIOD, &GPIO_InitStructure);

// NWAIT-PD6 for NOR memory Ready/Busy signal */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);

/*-- FSMC Configuration ----------------------------------------------------*/
// p.FSMC_AddressSetupTime = 2;
// p.FSMC_AddressHoldTime = 0;
// p.FSMC_DataSetupTime = 5;//3;
// p.FSMC_BusTurnAroundDuration = 0;
// p.FSMC_CLKDivision = 0;
// p.FSMC_DataLatency = 0;

p.FSMC_AddressSetupTime = 15;
p.FSMC_AddressHoldTime = 15;
p.FSMC_DataSetupTime = 255;//3;
p.FSMC_BusTurnAroundDuration = 15;
p.FSMC_CLKDivision = 16;
p.FSMC_DataLatency = 17;
p.FSMC_AccessMode = FSMC_AccessMode_B;

FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM1;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;

FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);

/* Enable FSMC Bank1_NOR Bank */
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM1, ENABLE);
}

 

[mƎALLEm]

Hello,

There is no problem to use external NOR and SRAM connected via FSMC.

STM3210E-EVAL board has already that configuration:

Detailed schematics on that link.

It could be something related to your NOR Flash config (timing etc ..). Did you succeed by configuring only NOR without the SRAM?

[selaslan1]

Yes actually We have designed our board according to STM32-EVAL board which you have referenced.

We just forgotten pull upresistors for chip enable pins (NE1 and NE2)

I have configured both SRAM and NOR flash.

Actually I have tested the flash only (without SRAM), no change

 

 

 

[Tesla DeLorean]

>>What is wrong?

Hard / Impossible to tell with the thoroughness of the presentation..

Yes, you should be able to have multiple devices on the bus, they should present at different address regions, ie 0x60000000, 0x64000000, etc.

Each device has it's own chip select and timing.

The EVAL series boards should provide worked examples of how these come together.

The NOR FLASH, you're going to have to probe with magic address/data sequences to read JEDEC ID, program, etc.

You'll need to review the M29W640GT data sheet, and build a simple BSP to probe and program. The blank IC should return 0xFF data patterns.

 

[selaslan1]

We are waiting STM32-EVAL board from our other R&D office. We'll test the code in STM32-EVAL.

I'll update you.