STM32F103 LSE load capacitance calculations (RTC)

[Cgelectronics]

Hello STM Comunity, 

I am making this post because I have reviewed many reference schematics for the use of the STM32F103C8T6, and in most of them, I see that they use 20pF load capacitors for the LSE circuit.

The datasheet literally states that the value of the load capacitors should not exceed 15pF (considering that both are of the same value) and that the load capacitance of the quartz crystal should not exceed 7pF.

It also indicates the maximun LSE driving current (1,4uA) and the oscillator transconductance gm (5uA/V)

To illustrate this a bit, I have taken as an example a crystal with the following characteristics:

• Nominal frequency (f_nom): 32,768 Khz
• Drive level (DL): 0,5uW
• Load capacitance (CL) : 7pF
• Motional resistance (ESR) typ: 65Kohm
• Motional capacitance (C1): 6,4fF
• Shunt capacitance (C0): 1,3pF
• Motional inductance (L1):3,7kH

 

The application note AN2867 (Guidelines for oscillator design on STM8AF/AL/S, and STM32 MCUs/MPUs) shows all the calculations needed to select the correct value of the capacitors for the LSE crystal.

Next, I am going to show an example of how I performed the calculations using a quartz crystal that has the maximum load capacitance allowed according to the datasheet. I hope this information will be useful for you in the future.

Assuming that Cstray in double-sided circuits ranges between 1pF and 2pF according to this post: https://community.st.com/t5/stm32-mcus-boards-and-hardware/stm32f103c8-production-board-schematic/m-p/140427#M4538 the formula would be like thefollowing (CStray = 1pf):

Oscillator trasconductance:

 < 1uA/V

   > 5

Drive level:

 < 0,5uW

Taking all of the above into account and according to the calculations I have performed, the maximum capacity that the crystal load capacitors could have would be 14pF assuming that C_stray is 0 and that the quartz crystal has a CL of 7pF. Therefore, I don't understand why the schematics have 20pF capacitors for the LSE circuit. Below, I indicate some reference schematics:

• https://stm32-base.org/assets/pdf/boards/original-schematic-STM32F103C8T6-Black_Board.pdf
• https://stm32-base.org/assets/pdf/boards/original-schematic-STM32F103C8T6-STM32_Smart_V2.0.pdf
• https://stm32-base.org/assets/pdf/boards/original-schematic-STM32F103C8T6-Blue_Pill.pdf

Could someone in this community explain if it is my mistake, or are the schematics I indicated above incorrect?

Thanks in advance!

 

 

 

 

 

 

 

 

[AScha.3]

Hi,

1. your (almost) right.

2. smart_V2 board uses 2x 15P - so this is ok. right ?

3. see STM nucleo F103 :

-> specified crystal, 4.3P load. As it should be.

 

All other schematics you linked are Chinese-unknown-origin boards - so what you expect ?

They just copy some standard circuit from each other, no matter, good or bad or even not working. So you get, what you paid for...

[Cgelectronics]

Hello @AScha.3 ,

Point number 2 doesn't seem to be very aligned with the information that can be extracted from the microcontroller's datasheet or reference manual, although according to @STOne-32  explanation, using capacitors with a value of 15pF could be justified as long as the GM is below 1.
In any case, knowing what I know now, I would follow the rules and never use capacitors above 14pF.
It is true that many reference designs of questionable origin violate this rule, although if in the end the GM (Gain Margin) is below 1, the use of load capacitance higher than 15pF could be justified.

Thanks for your response.

[STOne-32]

Dear @Cgelectronics ,

 

Thank you for the detailed question and here is my reply - I was among the original contributors on the very first AN2867 and also we produced billions of STM32 MCUs where most of our customers are using our LSE with the very famous tunning  fork quartz 32,768KHz . Before our Introduction of STM32F103 MCU in 2007, the reference crystal CL is at 12,5pF to have a robust industrial and very low pullability Clock . STM32F103 is optimized for low power operations including VBAT mode and added a circuitry that supports maximum CL = 7pF , believe me it was a revolution at that time … no more now and we worked with all crystal partners to have standard parts crystal and high runner at market with CL=7pF , 6 pF and compact size for PCB . Today they are standards.

Back to you question : “Taking all of the above into account and according to the calculations I have performed, the maximum capacity that the crystal load capacitors could have would be 14pF assuming that C_stray is 0 and that the quartz crystal has a CL of 7pF. Therefore, I don't understand why the schematics have 20pF capacitors for the LSE circuit”

 

=> This absolutely correct and right . Never CL1 and CL2 should exceed 14pF for a 7pF crystal  and in reality with a Cs=2pF it should not exceed 10pF to operate as you expect.

That means the real frequency will be the closed in terms of PPM to 32,768KHz  and so drift will be minimal.

Taking into account of course the startup condition of GM and Gm crit as you explained.

using 20pF will work if GM is satisfied in nominal condition as a crystal ESR is always typical and our formula is based on ESR Max computation - high or very low temperature and all VDD range 2Volts to 3,6Volts. But if the crystal CL=7pF the oscillation frequency will be slower than 32,768KHz and with +100 to 300 PPM is some cases instead of +50PPM .. many applications do not care of the frequency drift such as consumer as they calibrate it by digital with RTC registers or synchronize with BLE etc. 

Hope it helps you 

Ciao

STOne-32

 

[Cgelectronics]

Hi @STOne-32 , sorry for not responding all this time. I'm glad to know that I was on the right track and that my calculations are accurate. After reading your response, I have no doubts about it. It's great to have people with a background who have also contributed from the beginning to the topic I asked about. I hope that anyone with doubts about calculating the load capacitance of quartz oscillators can resolve them by reading this post.
Thank you very much!"