STM32F105VCT micro GPIO input thresholds
We are using STM32F105VCT micro in our product from many years.
In the recent hardwares, we have seen that input logic level is changing only with 200mv change.
When the input voltage to any port pin is crossing 1.5 we are seeing as logic level 1, when input voltage reduces more than 1.3 volts we see it as logic level 0, only 200mv gap. This is causing smaller noise on the input pin causing edge detect triggers in the firmware.
With our old batch of micros we see input logic level 1 at 1.7v and logic level 0 at 1.3v. So gap is 400mv
As per the data sheet we should see gap 600mv approx between two logic levels
Our VDD is 3.3 V (CMOS)
As per this VIL max threshold should be 1.136V
VH min threshold should be 1.833V
There is a gap of 697mv theoretically.
Can you please let us know what is the reason behind this, why in both cases it is not matching the data sheet?
