AFAIK the 'F405/407 is (almost) perfectly upward compatible with 'F205/207 (with the pinout caveats for the 144-pin package, see below).
This was a conscious decision of ST when designing the first 'F4 line, so that the risk with using the then new Cortex-M4 core would be minimized, i.e. that users could develop on the 'F2 until the 'F4 is ready, and then migrate seamlessly.
For example, while the 'F2 RTC has only the older coarse calibration, the 'F4 RTC not only has the newer fine calibration but it also retained the coarse calibration (so as the only STM32 family it has both).
So, *binaries* which run on 'F2 should run without any hesitation on 'F4 in the same hardware, too - provided the hardware caters for the pinout caveats in some packages. For the 144-pin package you are going to use, AFAIK there are two differences: pin 30 (capacitor only for STM32F2xx and VDD for STM32F4xx), and pin 143 (marked as "Reserved for Future Use" (RFU) for STM32F2xx and to be connected to any level or left floating; and PDR_ON, to be connected to VDD in most designs for STM32F4xx). See the (slightly badly annotated) Compatible board design between STM32F10xx/STM32F2/STM32F40xxx for LQFP144 package figure in the STM32F4xx datasheet.
Of course, if you will run the 'F4 at higher system clock frequency, you would need to use different FLASH waitstates, there will be different power consumption. There may also be differences in mutual timing of peripherals (for example the UART baudrate divider will be different) - and this, depending on details of your program, it may for example reveal an unexpected relationship between peripherals and actions which was not present with lower system clock.
And of course there may be minor differences in the very minute details such as exact power consumption, or details I am not aware of. At the end of the day, it's still your responsibility to check if the application is working as expected after the migration.
JW
