STM32F303 bypass the lack of DMA trigger via GPIO

[PKurz.1]

I use TIM1 to generate PWM. I want to stop it by the BRK signal. I need to delay the BRK signal so that it works only at the end of the PWM period.
The delay will be implemented on TIM3 in OPM mode, and for this I need to synchronize the CNT of both timers without any delay.
Is it possible to trigger DMA transmission on the rising edge of the signal entering directly to TI1FP1 TIM3 and copy the CNT from TIM1 to TIM3?

 

regards

[waclawek.jan]

> Is it possible to trigger DMA transmission on the rising edge of the signal entering directly to TI1FP1

Yes, that's standard Input Capture, thus TIM3_CH1 triggered DMA.

But note, that latencies are involved. DMA is no magic. You may want to have the two timers running synchronously all the time from the start, for which the master-slave connection may be more suitable (and it's to certain extent is there exactly for that purpose).

You may also want to reconsider the whole idea. Point of BREAK is, that it's asynchronous, thus fast; so you are somewhat going against the grain of it.  I'm not sure how do you want to accomplish BREAK to be generated by TIM3.

One way to stop timer at the end of cycle is to have ARR preloaded (ARPE = 0), and make the external signal trigger transfer of value 0 to ARR.

JW

 

[PKurz.1]

> One way to stop timer at the end of cycle is to have ARR preloaded (ARPE = 0), and make the external signal trigger transfer of value 0 to ARR.

Will this put the outputs in a high impedance state?

 

> But note, that latencies are involved. DMA is no magic.

There will be no faster solution.

 

> I'm not sure how do you want to accomplish BREAK to be generated by TIM3.

I will configure the TIM3 output as OC and pull the resistor to my break signal. Then I will connect to the BRK TIM1 input.

 

I want this solution to be fast and, if possible, completely hardware-based.

 

This is how it initializes it, but it doesn't look like it's going to work.

if (HAL_TIM_OC_Start(&htim1, TIM_CHANNEL_1) != HAL_OK)
{
	/* Initialization Error */
	Error_Handler();
}
if (HAL_TIMEx_OCN_Start(&htim1, TIM_CHANNEL_1) != HAL_OK)
{
	/* Initialization Error */
	Error_Handler();
}
if (HAL_TIM_IC_Start_IT(&htim3, TIM_CHANNEL_1) != HAL_OK)
{
	/* Initialization Error */
	Error_Handler();
}
if (HAL_DMA_Start(htim3.hdma[TIM_DMA_ID_CC1], (uint32_t) &htim1.Instance->CNT, 
 (uint32_t) &htim3.Instance->CNT,
		 TIM_DMABURSTLENGTH_1TRANSFER) != HAL_OK)
{
	/* Initialization Error */
	Error_Handler();
}

 

[waclawek.jan]

> > One way to stop timer at the end of cycle is to have ARR preloaded (ARPE = 0), and make the external signal trigger transfer of value 0 to ARR.

> Will this put the outputs in a high impedance state?

Indeed, no.

Do you need the outputs to end in high impedance state, or do you need them in some particular state (high, low, what combination)?

 

> > I'm not sure how do you want to accomplish BREAK to be generated by TIM3.

> I will configure the TIM3 output as OC and pull the resistor to my break signal. Then I will connect to the BRK TIM1 input.

Sounds cludgy.

Note, that Cube/HAL may get into way more than help, if you do anything which is not deemed "usual" by Cube's authors, whatever it is. I don't Cube/HAL.

JW

 

[waclawek.jan]

At this point, you got me confused, as you've never mentioned need for "restore".

Can you please sketch a timing diagram describing what you want you achieve? We may come up with something, but not if the target is uncertain and changing.

JW