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charlesa
Explorer
July 22, 2024
Solved

STM32F303xC BOOT1 bit and voltage difference

  • July 22, 2024
  • 1 reply
  • 950 views

Hi all,
I am currently designing a board based around the STM32F303xC MCU, and had a few questions regarding information on the datasheet.

- For boot modes, the data sheet states the following:
"At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
• Boot from user Flash
• Boot from system memory
• Boot from embedded SRAM
The boot loader is located in the system memory. It is used to reprogram the Flash memory
by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU
(device firmware upgrade)."

How would the BOOT1 option bit be set? I do not see a pin or specific firmware instructions for where BOOT1's option bit is located. I plan to boot from Flash memory by sending data through USB.

- In the datasheet, Table 21 states there can be a maximum V_DD-V_DDA voltage difference of 0.4 V. All my analog inputs can output a maximum of 2.0 V, and ideally I would like to power the MCU with 3.3 V. Would there be issues with these voltages, as it exceeds the 0.4 V limit? If so, would it be better to increase the V_DDA, or decrease the V_DD to be around 2.4 V? I am concerned about any issues with the MCU at this lower voltage. Likewise, how would the V_REF+ be affected in this situation.

Any clarification would be appreciated. Thank you.

    This topic has been closed for replies.
    Best answer by TDK

    > How would the BOOT1 option bit be set?

    The nBOOT1 option bit is within the option bytes. Use STM32CubeProgrammer to set the option bytes. Connect and select the "OB" tab.

    TDK_0-1721698777716.png

     

     

    > - In the datasheet, Table 21 states there can be a maximum V_DD-V_DDA voltage difference of 0.4 V. All my analog inputs can output a maximum of 2.0 V, and ideally I would like to power the MCU with 3.3 V. Would there be issues with these voltages, as it exceeds the 0.4 V limit? If so, would it be better to increase the V_DDA, or decrease the V_DD to be around 2.4 V? I am concerned about any issues with the MCU at this lower voltage. Likewise, how would the V_REF+ be affected in this situation.

    Per the datasheet, VDDA = 2.0 and VDD = 3.3 doesn't work due to the restriction you found. You can reduce VDD without affecting much except the chip will not be able to run as fast. If max clock speed is a priority, keep it at 3.3V.

    Generally it's not tenable to supply VDD and VDDA separately due to this, but it can be done if the restrictions are followed. Easier to put a ferrite bead before VDDA and connect them to the same supply.

    VREF+ is separate from VDDA but also must be within 0.4V of VDDA.

     

    For your application, two options:

    • VDD = VDDA = 3.3 V will give higher possible clock speeds but generally worse analog performance due to only using a portion of the overall range.
    • VDD = VDDA = 2.4 V (or so) will give better analog performance but lower max clock speeds. You will also need to ensure external signals are compatible with 2.4 V logic rather than the more common 3.3 V.

    1 reply

    T
    TDKAnswer
    Super User
    July 23, 2024

    > How would the BOOT1 option bit be set?

    The nBOOT1 option bit is within the option bytes. Use STM32CubeProgrammer to set the option bytes. Connect and select the "OB" tab.

    TDK_0-1721698777716.png

     

     

    > - In the datasheet, Table 21 states there can be a maximum V_DD-V_DDA voltage difference of 0.4 V. All my analog inputs can output a maximum of 2.0 V, and ideally I would like to power the MCU with 3.3 V. Would there be issues with these voltages, as it exceeds the 0.4 V limit? If so, would it be better to increase the V_DDA, or decrease the V_DD to be around 2.4 V? I am concerned about any issues with the MCU at this lower voltage. Likewise, how would the V_REF+ be affected in this situation.

    Per the datasheet, VDDA = 2.0 and VDD = 3.3 doesn't work due to the restriction you found. You can reduce VDD without affecting much except the chip will not be able to run as fast. If max clock speed is a priority, keep it at 3.3V.

    Generally it's not tenable to supply VDD and VDDA separately due to this, but it can be done if the restrictions are followed. Easier to put a ferrite bead before VDDA and connect them to the same supply.

    VREF+ is separate from VDDA but also must be within 0.4V of VDDA.

     

    For your application, two options:

    • VDD = VDDA = 3.3 V will give higher possible clock speeds but generally worse analog performance due to only using a portion of the overall range.
    • VDD = VDDA = 2.4 V (or so) will give better analog performance but lower max clock speeds. You will also need to ensure external signals are compatible with 2.4 V logic rather than the more common 3.3 V.
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