STM32F373 Sigma Delta ADC: Filter Specs & FFT plots ?

[LCE]

Heyho,

for a new project I need an MCU with 2 channels of 16bit / 50kHz ADC.

It looks like the F373's sigma delta ADC (SDADC) might be good enough (it will be calibrated for accuracy anyway).

But I haven't found any info about the SDADC's digital low pass / decimation filter, and no FFT plots.

Can anybody help me out, and/or share their experience with that ADC?

[tjaekel]

"The used filter topology that ensures the low-pass stage is Sinc3.":

https://www.st.com/resource/en/application_note/an4207-getting-started-with-stm32f3738xxx-sdadc-sigmadelta-adc-stmicroelectronics.pdf

"Filter the SDADC samples using a bandpass FIR filter" (mentioned in the same AN).

Measure it yourself: it depends anyway on the "noise free" reference signal (and power ripples of your power supply). The FFT makes just real sense with your real signal.
BTW: why do you assume a decimation involved? (1bit delta-sigma do not have a decimation, for my understanding)

[LCE]

Hello @tjaekel ,

thanks for the pdf, sinc3 it is. Amazing that I didn't find that in all my googling efforts!

But no filter plot, not even in the AN. That's another example how ST's documentation could be improved.

But okay, sinc3 says it all, rather crappy, but probably good enough, and better than the 12 bit ADC (?).

"Measure it yourself":
yes, I'm a big fan of that, but no: no Nucleo available, and sometimes I just want to trust a manufacturer's documentation - if available...
Power supply noise will probably not be an issue, as this would be an extra in a mixed-signal, low noise measurement system with low noise supply voltages.

Decimation:
the low-pass filter after the sigma-delta stage(s) is actually a decimation filter, because it "decimates = lowers" the oversampled 1-bit stream to the target sampling rate and target bit resolution.