STM32F4 SPI high level 5V

[Scarlet]

Sorry, I have another question to ask everyone. I'm currently using the Nucleo F429ZI with SPI interface to receive 12-bit encoded data from another ADC. The Vdrive of that ADC can provide 3.3V or 5V for driving. However, the high level of the STM32F429ZIT6 is 3.3V. If I want the SPI high level to be 5V, what methods can I use to achieve this?

Originally, I was researching GPIO's Open Drain to use an external 5V to accomplish this, but in CubeIDE, the SPI is set to Push-Pull. So I would like to ask, when using STM32, how can I achieve a 5V high level if the SPI requires it?

 

[Imen.D]

Hello @Scarlet ,

It's possible to setup the configuration described and speaking about 5V tolerant pins only in input mode.

When the output mode is enabled, the GPIO is no more 5V tolerant.

It could work based on next principle for I2C. Taking into consideration that problematic could be difference between VDD and VDDx, which should never exceed 3.6 V:

 

[Scarlet]

Hi @Imen.D,

Originally, I planned to use the Open Drain method to provide external 5V, but in CubeIDE, the SPI setting is configured as Push Pull. I cannot guarantee that when outputting a high level, the 5V won't flow to the STM32 VDD 3.3V.

[Uwe Bonnes]

Open drain and about 50 Mhz is probably no good combination, either current hungry  or with bad waveforms.

[AScha.3]

>The Vdrive of that ADC can provide 3.3V 

So use this 3v3 setting and you are on the safe side.

>If I want the SPI high level to be 5V, what methods can I use to achieve this?

Only for inputs (here) can use a voltage divider, like 2k - 3k3 -gnd. So input at 3v3 max.

Or a 5v tolerant gate as level shifter at 3v3 VDD (VHC or UHC series have such ).

[Scarlet]

Or a 5v tolerant gate as level shifter at 3v3 VDD (VHC or UHC series have such ).

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I will check the level shifter aspect. I plan to use the MAX14850AEE for voltage conversion, but this is not the optimal solution. However, I will further research this area. Thanks.

 

Only for inputs (here) can use a voltage divider, like 2k - 3k3 -gnd. So input at 3v3 max.

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The voltage divider is like this?:

 

 

 

[AScha.3]

 

>The voltage divider is like this?:   yes, but without the short to 5V . :)

But need lower impedance resistors, at 2k /3k3 it might work up to 10MHz - but never 50MHz.

+

as level shifter gates i use something like this :

SN74LVC1G86   (single XOR gate ; at mouser 20ct , 595-SN74LVC1G86DCKR )

so need one for every line :

At 50MHz this is the way to go ; LVC gate can switch in 1.3ns at 3v3 (50pF load), so perfect here.

[Andrew Neil]

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@Scarlet wrote:

The Vdrive of that ADC can provide 3.3V or 5V for driving.

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So why not just use the 3.3V option ?

 

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@Scarlet wrote:

However, the high level of the STM32F429ZIT6 is 3.3V.

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Indeed - so, again, why not just use the 3.3V option in your ADC?

[Scarlet]

Because this ADC can use a higher SPI frequency with a Vdrive of 5V, I want to try if it's possible to reduce processing time.

 

[mƎALLEm]

Hello,

What is the part number of that ADC? Keeping the IOs as output push-pull, you don't have to add any external hardware if VIHmin (ADC IOs) < VDD of your MCU. 

Most of STM32 IOs are 5 volt tolerant. You need just to check the pin (FT or not).

You can attach the ADC datasheet so we can confirm.

 

[Scarlet]

I used the ADC is AD7366[1].

If I want to use a higher SPI frequency, I need to provide Vdrive 5V, but the MCU output high is 3.3V, which is less than 0.7 * 5V ADC input high voltage.

 

[1] AD7366 datasheet

[mƎALLEm]

Looking at the ADC’s datasheet page 4, VINH min = 0.7 x Vdrive = 3.5V > VDD MCU. So indeed you need to adapt the voltage of the IO externally in the direction from STM32 to the ADC.

[David Littell]

How fast do you intend to run /CNVST?

[Scarlet]

@David Littell 

Are you asking how soon after completing SPI reception, how fast run the next CNVST?
Currently still in testing, theoretically aiming for as soon as possible.