STM32F427 PWM on 40 pins with DMA and BSRR

[Vach23]

Hi,

I need to generate ~8khz PWM on 40 pins with at least 1% resolution. I was thinking about solution using GPIO ports D,G,F and DMA2 streams 1,2, 7 which are all triggered by TIM8 (TIM8_UP, TIM8_CH1, TIM8_CH4/TRIG/COM).

I am worried about the data transfer speed of the DMA. 8khz, with 1% resolution means 0,8Mhz x 3 ports = 2,4Mhz DMA streams. Reffering to documentation it takes about 8 APB clock cycles to process and perform DMA transfer which means that it takes about ~20M clockcycles/sec and APB2 is running currently at 84Mhz. This seems quite a lot and Im worried about saturating the bus.

Can someone correct me please? How big of a problem this could potentially be? How fast i can go with this?

Thank you very much in advance!

[TDK]

DMA transfers at 2.4 MHz are definitely at the upper end of what is possible but should be doable if that's the only thing using the bus.

But at that update rate, you're going to run out of memory unless what you're sending is very short in duration and cyclical.

[waclawek.jan]

> Reffering to documentation it takes about 8 APB clock cycles to process and perform DMA transfer

What documentation says this? Are you aware of the differences between the single-port DMA (in 'F1/'F0/'F3/'L4/'G0/'G4 etc.) vs. the dual-port DMA ('F2/'F4/'F7)?

Also, in this particular case, i.e. transfer from SRAM (on AHB bus) to GPIO (on a different AHB bus), there's absolutely no involvement of APB, thus APB clock in the transfer duration.

Your budget is some 200+ cycles per three transfers, that's plenty.

JW