STM32F429 timer Question

[Franksterb92]

im confused about the TIMPRE bit in the RCC_DCKCFGR does it only effect the apb1 and not apb2 timers cause the way it describes this bit it acts like the apb2  can be times 4 because it says PPREx so 1 or 2  but on cube mx im noticing when u enable the timer prescaler the only timers effected are the apb1 timers 

[waclawek.jan]

The Reference Manual (RM) is more authoritative than CubeMX.

I don't use CubeMX. Show how RCC_DCKCFGR.TIMPRE is set in CubeMX and how that does/does not affect the timer clocks.

JW

[Sarra.S]

Hello @Franksterb92, 

This explanation is based on RM description: 

if TIMPRE = 0:

• If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1, then TIMxCLK = PCLKx
• Otherwise, the timer clock frequencies are set to twice the frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx

if TIMPRE = 1:

• If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a division factor of 1, 2, or 4, then TIMxCLK = HCLK
• Otherwise, the timer clock frequencies are set to four times the frequency of the APB domain to which the timers are connected: TIMxCLK = 4xPCLKx

Could you describe a concrete use case where you are noticing that only APB1 timers are affected? 

[Franksterb92]

it just confusing that it says that apb2 can be 4 times which would be 360mhz if hclk == 168mhz ... see what im saying 

[Tesla DeLorean]

Yeah, I'm hard pressed to see it doing that too.

The PLL usually has a DIV2 out of the VCO, because it's a pulse-generator, and all the logic for the MCU/Peripheral are predicated on a 50/50 duty clock.

I think what's trying to be communicated is that if the APB is divided down the TIM can be faster, by skipping dividers in the HCLK/SYSCLK chains, not that it's actually multiplying anything.

Can be 168 MHz, not 336 MHz (or 180/360 for the higher clocking option), when the APBx is 42 MHz