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neetha_jyo98
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December 1, 2023
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STM32F767 QSPI Slave

  • December 1, 2023
  • 2 replies
  • 2497 views

Hi,

I have the following questions about QSPI in STM32F767:
1.  Is it possible to configure the board as QSPI Slave? I could not find any option in the CubeMX Tool to choose between master and slave. 
2. Is the QSPI peripheral of this board strictly limited to interfacing only QSPI flash devices? In other words, is it possible to interface a QSPI slave which is not a flash device?
3. Is it possible to configure the normal SPI peripheral to work as QSPI?

 

I referred the below link, which states that QSPI is strictly master-driven. But I would like to confirm this statement.

https://community.st.com/t5/stm32-mcus-products/is-it-possible-to-configure-the-qspi-as-slave-to-receive-data/td-p/363586

 

@Jaroslav BECKA 

    This topic has been closed for replies.
    Best answer by Tesla DeLorean

    >>But I would like to confirm this statement.

    By someone repeating it to you, or you actually confirming it be reading the manuals and trying a couple of things to rule operation in or out?

    You can use anything that meets the protocol requirements, like a FPGA/CPLD, RAM, NAND FLASH, NOR FLASH, etc. The F7 supports memory-mapping for READ operations, here consider this just using a command template that works normally, and the STM32 peripheral just masks and stuffs in the ADDRESS of the access in normal operation. You need to ABORT the QSPI to get it out of this mode and back to one where you can send commands.

    No, it doesn't support SLAVE operation, bit to fast and awkward to do in any case, it's a protocol better implemented completely in HW and state-machines, see CPLD/FPGA for how you'd approach a device running at 50-100 MHz type rates, it's not SW and not interrupts..

    2 replies

    M
    mƎALLEm
    Technical Moderator
    December 1, 2023

    Hello @neetha_jyo98 ,

     

    For your first question. Yes, it's only QSPI master interface.

      T
      Tesla DeLoreanAnswer
      Graduate II
      December 1, 2023

      >>But I would like to confirm this statement.

      By someone repeating it to you, or you actually confirming it be reading the manuals and trying a couple of things to rule operation in or out?

      You can use anything that meets the protocol requirements, like a FPGA/CPLD, RAM, NAND FLASH, NOR FLASH, etc. The F7 supports memory-mapping for READ operations, here consider this just using a command template that works normally, and the STM32 peripheral just masks and stuffs in the ADDRESS of the access in normal operation. You need to ABORT the QSPI to get it out of this mode and back to one where you can send commands.

      No, it doesn't support SLAVE operation, bit to fast and awkward to do in any case, it's a protocol better implemented completely in HW and state-machines, see CPLD/FPGA for how you'd approach a device running at 50-100 MHz type rates, it's not SW and not interrupts..

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