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Visitor II
January 29, 2025
Question

STM32F7xx JPEG Encoder DMA ST example works only in DTCM Ram

  • January 29, 2025
  • 1 reply
  • 997 views

Hello to all,

We are trying to take over the JPEG_EncodingFromFLASH_DMA example from ST running on the STM32F769I_EVAL board.
The original ST software runs fine on the board.
However all the ram data is linked starting from 0x20000000, which is the tightly coupled DTCM Ram.
As in our project the DTCM Ram will be used for Stack and Heap because of its speed, we recompiled the ST example to link the data into 0x20020000. (This SRAM is accessible via the busmatrix only)
If we do this the pixel data in the jpg image is distorted. It is still possible to recognize the original picture, but with lots of pixel erros in it.

So the question is: Why is it essential to have the Input/Output DMA buffers (for feeding the JPEG encoder with data) located in the fast DTCM Ram? When the JPEG encoder triggers a DMA request how is it synchronized if the DMA cannot become a busmaster in the busmatrix immediately?

As the fault can be provoked easily by just linking the data of the untouched! example software to 0x20020000 instead of 0x20000000, I am hoping to get answers to my questions.

Have a nice day

Andy

 

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    1 reply

    Technical Moderator
    January 29, 2025

    Hello,

    Did you enable the D-cache for SRAM1 (0x20020000)?

    andywild2Author
    Visitor II
    January 29, 2025

    Hello SofLit,

    sure the cache is enabled!
    To say it again: I am not talking about my software, but the ST example for JPEG on GitHub.
    Here is the link:
    https://github.com/STMicroelectronics/STM32CubeF7/tree/master/Projects/STM32F769I_EVAL/Examples/JPEG/JPEG_EncodingFromFLASH_DMA

    In main.c you can see that CPU_CACHE_Enable(); is called.

     

    andywild2Author
    Visitor II
    January 29, 2025

    In the meantime I found this post:
    https://community.st.com/t5/stm32-mcus-touchgfx-and-gui/h-w-jpeg-must-use-dtcm-sram-not-documented-anywhere/td-p/242899

    So I will play with the MPU in terms of cache for the SRAM1