STM32G050 Debug with IWDG enabled

[BlazejK]

I enabled IWDG on my STM32G050C8T6 and it works correctly but I also want to be able to debug the MCU with IWDG enabled. According to the MCU family's reference manual I should set  bit 12 (DBG_IWDG_STOP) of DBG APB freeze register 1 (DBG_APB_FZ1) to disable IWDG clock counter when the core is halted.

The DBG APB freeze register 1 can be written by debugger under system reset.

But I do not know how to write to this register. I tried to change it using STM32CubeProgrammer but it does not work.

I also tried to do this using st-link utility and gdb but the DBG_APB_FZ1 is still 0.

How to set this register so I can debug my device with IWDG enabled?

 

 

[Sarra.S]

Hello @BlazejK, 

You can do this either with STM32Cubeprogrammer, through the OB tab, look for the DBG_APB_FZ1 register and set bit 12 (DBG_IWDG_STOP), apply the changes and reset the device.

Or, you can do that by SW, by writing a mask to the DBGMCU register: 

DBGMCU->APB1FZ1 |= (1 << 12); 

[BlazejK]

Hello @Sarra.S 

Thank you for replying.

Unfortunately there is no DBG_APB_FZ1 register in OB tab.

And trying to set this bit in software was the first thing I tried to do since I have already used this option in other STM32 device family (and it was working there) but with the current MCU when I set the appropriate bit and then read the register the register is 0 (debug variable equals 0).

 SET_BIT( DBG->APBFZ1, DBG_APB_FZ1_DBG_IWDG_STOP );
 uint32_t debug = DBG->APBFZ1;