STM32G0B0CE/KE/RE/VE device errata

[matsuami]

There is a description in the errata(STM32G0B0CE/KE/RE/VE device errata) as shown below, but could you please provide a waveform diagram to show which part of the glitch is dangerous?

 

USART

2.10.1 Data corruption due to noisy receive line

Description

In UART mode with oversampling by 8 or 16 and with 1 or 2 stop bits, the received data may be corrupted if a glitch to zero shorter than the half-bit occurs on the receive line within the second half of the stop bit.

 

[Imen.D]

Hello @matsuami and welcome to the Community :)

Why do you need the waveform diagram?

As mentioned in the limitation description, the issue happens when the glitch to zero has a duration less than a half bit duration and arrives during the second half of the stop bit.

Nothing else special needs to be shown in waveform diagram.

[matsuami]

Hello Imen.D

Thank you for your answer.

I wanted the meaning of "he second half of the stop bit" clarified.

In the case of a 2stop bit setting,

① Is it the latter half bit of the first stop bit?
② Is it the latter half bit of the second stop bit?
③ Or is the glitch in the latter half bit NG regardless of which stop bit it is?

Which of ① to ③ is correct?

[waclawek.jan]

Here is a real-world example of the problem:

The logic analyzer was set not to suppress glitches, so - unlike normal UARTs - it considered the glitch to be startbit of the next byte.

While the logic analyzer correctly decoded the byte just before the glitch as 0xAC, the UART in STM32 (in this case, 'L431, but it's the same as in 'G0x) received it incorrectly as 0xD6.

JW

[matsuami]

Hello waclawek.jan

Thank you for providing an example of the error.

Best regards

[waclawek.jan]

Hi @matsuami ,

> In the case of a 2stop bit setting

I don't know. But number of stop bits are a setting of the transmitter, while the problem is in the receiver, so I'd say, the number of stopbits in the receiver does not change the behaviour.

In other words, if the glitch happens in the second half of 1st stopbit, the problem occurs; if later, the problem won't occur.

JW

[matsuami]

Thank you for your valuable post.

If we set it to 2stop bit mode, the number of bits in the communications protocol must be matched on the sender and receiver sides for communication to be established.
That means the receiver also needs to be set, and the number of bits the receiver monitors will be different from when it is in 1stop bit mode, so it seems like the behavior of the receiver will also change.

So could you please explain why a glitch in only the second bit of 2 stop bits does not lead to data corruption?
if there is a glitch in only the second bit of the 2stop bit, will an error flag be set?
In other words, will I not get erroneous data?

Best regards

[waclawek.jan]

> the number of bits in the communications protocol must be matched on the sender and receiver sides for communication to be established

No.

This basically says, that the 2nd stop bit is entirely ignored in the receiver.

JW

 

[matsuami]

Hello waclawek.jan

Thank you for providing the excerpt from the reference manual.

I could understand that in 2 stop bit mode, if there is no error in the first BIT, then readable normal data is written to the FIFO at that point.

So, even if there is a glitch in the second BIT, it is impossible for corrupted data to be written to the data register.

You're a real guru. Thank you.