STM32G0B1 FDCAN and bit timing
Hi,
I would like to use the FDCAN peripheral of the STM32G0B1, for CAN2.0B.
Coming from the F0 CAN peripheral, I can understand most of the new peripheral easily.
However, for the bit timing, per FDCAN specification, there are 2 bit times: the nominal (like standard CAN) and the one for the fast data. So far so good.
For the nominal bit time, it is written at the bottom of the page 1232 of the RM0444 (36.4.7) that the CAN bit time may (not must ?) be programmed in the range of 4 to 81 time quanta.
My questions are:
- This limitation is strange as the bit time is made of [NTSEG1 + NTSEG2 + 3] * tq, with NTSEG1/2 being as high as 255, 127 respectiveley, so well above 81.
- What happens if the total of bit quanta is equal to 3 or above 81 ?
- This limitation is not mentionned in the data bit time register. Is it also applicable ?
Best regards.
