STM32G4 and Timer channel 5&6

[Eiffel]

Currently i am writing my own MCAL drivers for G4 MCU's and i dont understand interrupts for timer channels 5&6. Lets assume Timer 1 where you can check interrupt status of CC of channels 5&6 in TIMx_SR on bits 16&17. But there is no mention about activation and deactivation in registers.

So how does it work? Is it activated randomly? 

[TDK]

I suspect that channels 5 and 6 are not able to cause interrupts. Not that they're only available as outputs. But otherwise the CC5IF and CC6IF bits act similar to CC1IF (i.e. get set on match).

 

HAL certainly agrees with this as channel 5 and 6 are not valid inputs to HAL_TIM_PWM_Start_DMA or HAL_TIM_PWM_Start_IT.

[Sarra.S]

Hello @Eiffel, 

For Timer 1 on STM32 MCUs, channels 5 and 6 do not generate interrupts, even though there are status bits for these channels in the TIMx_SR register, they are intended for polling purposes only. This means you can check these bits to see if an event has occurred, but you cannot configure the MCU to generate an interrupt based on these events (there are no corresponding interrupt enable bits in the TIM1_DIER register).

This behavior is a design choice.

Thank you! 

 

[Sarra.S]

Hello @Eiffel, 

Do you consider your question as answered?