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Visitor II
March 11, 2025
Solved

STM32G474 clock 170 MHz

  • March 11, 2025
  • 2 replies
  • 2680 views

Hello,

I use 25 MHz quarz (XRCGB25M000FAN00R0) together with 5.6 pF load capacitors. When I configure clock to 170MHz my program stuck here: while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U).

When I configure clock to 168.75 MHz, then everything work corectly. 

Can someone explain how this problem could be solved?

Thank you for answers.

Best regards

 

Configuration for 168.75MHz clock:

 

void SystemClock_Config(void)
{
 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

 /** Configure the main internal regulator output voltage
 */
 HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);

 /** Initializes the RCC Oscillators according to the specified parameters
 * in the RCC_OscInitTypeDef structure.
 */
 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2;
 RCC_OscInitStruct.PLL.PLLN = 27;
 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 {
 Error_Handler();
 }

 /** Initializes the CPU, AHB and APB buses clocks
 */
 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 {
 Error_Handler();
 }
}

 

 Configuration for 170 MHz clock:

 

void SystemClock_Config(void)
{
 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};

 /** Configure the main internal regulator output voltage
 */
 HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);

 /** Initializes the RCC Oscillators according to the specified parameters
 * in the RCC_OscInitTypeDef structure.
 */
 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV5;
 RCC_OscInitStruct.PLL.PLLN = 68;
 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
 RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
 RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 {
 Error_Handler();
 }

 /** Initializes the CPU, AHB and APB buses clocks
 */
 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;

 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
 {
 Error_Handler();
 }
}

 

 

    This topic has been closed for replies.
    Best answer by koyocik

    I found out problem. I have on the board op amps. One of them generates negative voltage which is applied to ADC input pin (I have zenner diode but after all I have there -0.75V). This negative voltage caused strange behaviour with clock settings. 

    Thank you all for the help on this topic!

    2 replies

    Technical Moderator
    March 11, 2025

    Hello,

    That's strange.  I don't see any issue in your clock init.

    Are you sure you have 25MHz on the OSC_IN/OSC_OUT pins?

    How did you calculate the load capacitors of 5.6 pF

    koyocikAuthor
    Visitor II
    March 11, 2025

    I used this equation: C1, C2 = 2*CL – 2*Cstray. 

    I tried use bigger capacitor value and lower but without any good result.

    Quarz is connected to pins 19 and 20 like below.

    1.png

     

     

    Technical Moderator
    March 11, 2025

    What CL and Cs values you have used for the calculation?

    Explorer
    March 11, 2025

    Apart from the capacitance issue discussed, there is an obvious difference in the PLLM and PLLN values for both cases.
    Check the datasheet that you don't exceed the maximal PLL frequency with your 170 MHz settings.

    koyocikAuthor
    Visitor II
    March 11, 2025

    I used CubeMX for clock configuration. Do you think that code is wrong generated?

    1.jpg