STM32G474 FDCAN tx buffers

[ULehm.1]

Since the description of the FDCAN controller in the reference manual of

the STM32G474 was not detailed enough, I looked around for more Information

and found the Application Note AN5348 ("FDCAN peripheral on STM32 devices ").

But that didn't make me feel more confused.- but that didn't answer my

questions, I'm even more confused now

At the moment I am busy sending CAN messages.

According to AN5348, the FDCAN has dedicated Tx buffers and optionally

a Tx FIFO or a Tx queue (Figure 4. CAN message RAM mapping.)

The FDCAN controller on the STM32G474 seems to be like a

minimal implementation of the controller described in the AN5348 -

obviously 32 Tx buffers are possible, but the STM32G474 has according to.

Reference Manuel only 3 of them. And as I understand I understand, they are

used as a TxFIFO or a TX queue - therefore there are no "dedicated" Tx buffer !?

Or can I simply use the 3 buffers in a detected manner by ignoring

the TXFQS registers and working only with registers TXBRP, TXBAR and TXBTO?

I am also not quite clear what the distinction Tx buffer

and Tx queue is all about (AN5348 / p.23): Figure 19. Mixed

configuration with dedicated Tx buffers and Tx queue)?

Actually I would like to use a buffer for cyclic

sending messages with high priority, a second buffer

should be feeded permanently from a software FIFO by means of an

interrupt, while the third shuold be keept free for later expansions -

I am not sure now, whether that can be implemented with the

FDCAN controller of the STM32G474?

[Johannes]

I have similar struggels with the documentation. What is the difference between FIFO and Queue? I assume that queue is equal to "buffers". you can put 3 messages into these buffers and they are processed according their priority. 
There is a HAL function to write into message ram (which contains the tx buffers) "FDCAN_CopyMessageToRAM". This takes a parameter "buffer index". But this function is static ( not accessible from outside the FDCAN module)

Another strange thing: 
There is a tx complete callback. You can register a function pointer to it. You get a callback, when a transmit is completed. You get the bitfield "TO" from Register FDCAN-TXBTO. This bitfield contains a bit per transmit buffer. These bit are set to 1, when a transmission is done. But there is no method to reset these bit except for sending another message with the same tx buffer. 

If I  use the following sequence:

• I send a message (it uses the first message buffer)
• I get a tx complete callback with the TO-bits = 1 (first buffer is done sending)
• I send another message (it uses the next message buffer =2 )
• I get a tx complete callback with TO-Bits = 3 (buffer 2 (OK) and buffer 1 (still set) 

That's strange. Is this meant to be that way? During the callback I cannot determin, which TX buffer has caused the callback, because the bits from other buffers keep being set.
What is the concept here? 

[Anon]

I am also struggling with the STM32G4 fdcan library, did you figure out if Rx and Tx use the same buffer? Have you managed to increase the Rx or Tx buffer size from 3?

Thanks for the info you have provided so far

[Johannes]

Hello Anon
As I recall, on the STM32G4 the TX Buffers are fixed to 3 (hardware). It cannot be changed

[czr]

hello Johannes

In STM32G4 Datasheet, "A 3-Kbyte message RAM memory implements filters, receive FIFOs, receive buffers,
transmit event FIFOs, transmit buffers. This message RAM is shared between the three
FDCAN modules"  But I can't find about "TX Buffers are fixed to 3" 

I want to change the TX buffer, Please tell me Where does "TX Buffers are fixed to 3" come from?

Many thanks, Bro