STM32G474RET Linker Question

[joego2124]

In the linker script provided by STM for STM32G474RETx, the memory section is:

MEMORY
{
 CCMSRAM (xrw) : ORIGIN = 0x10000000, LENGTH = 32K
 RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
 FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 512K
}

 But in the reference manual RM0440 section 2.4 page 88  it states that:

Category 3 devices feature up to 128 Kbytes SRAM:
• 80 Kbytes SRAM1 (mapped at address 0x2000 0000)
• 16 Kbytes SRAM2 (mapped at address 0x2001 4000)
• 32 Kbytes CCM SRAM (mapped at address 0x1000 0000 and end of SRAM2)

I'm confused as to why the RAM is declared as 128K when that's the combined total of SRAM1 + SRAM2 + CCMSRAM, and there's also CCNSRAM declared separately. Is it so that RAM covers all SRAM but you can also place specific things in the CCMSRAM section? 

[Radosław]

RAM region should have size 96K.

CCRAM have some limitarion  and with RAM to not create continuos  memory, 

 

Atribbute section will place you variable function in specyfic location. 

[KnarfB]

RM0440 Figure 2. Memory map shows three SRAM spaces acting as one continous data memory: SRAM1 + SRAM2 + CCM SRAM = 128 kB.

In addition, CCM SRAM is also available under adress 0x10000000. The ARM Cortex-M4 Technical Reference Manual has an explanation for that: 

ICode memory interface
Instruction fetches from Code memory space, 0x00000000 to 0x1FFFFFFF, are performed over this ... bus.

System interface
Instruction fetches, and data and debug accesses, to address ranges 0x20000000 to 0xDFFFFFFF and
0xE0100000 to 0xFFFFFFFF are performed over this ... bus.

You may place code in CCM SRAM for fast instruction fetch via ICode memory interface with parallel data access to the other SRAMs. If needed, you may place interrupt handlers and other time critical code in CCM SRAM for max. performance. If not needed, you may use CCM SRAM as additional data memory.

hth

KnarfB

[joego2124]

Thanks for the explaination. To further clarify, from RM0440 figure 1, it looks like CCM SRAM is connected to both instruction and data buses, as well as DMA peripherals:

 So this would mean I can place not only code but also initialize data in this area correct? And for the usage, I see under RM0440 2.4:

CCM SRAM is mapped at address 0x1000 0000.
Execution can be performed from CCM SRAM with maximum performance without any
remap thanks to access through ICode bus.
The CCM SRAM is aliased at address following the end of SRAM2 (0x2000 5800 for
category 2 devices, 0x2001 8000 for category 3 devices, 0x2001 8000 for category 4
devices), offering a continuous address space with the SRAM1 and SRAM2. CCM can be
accessed by DMA only by this aliased address.

Does this mean for non DMA usage I should be referencing to CCM SRAM in the linker script with the 0x10000000 address?

 

[KnarfB]

If your code perfomance is fine and you don't have any specific requirements, ignore that CCM SRAM is special.

Otherwise, I suggest studying Application note AN4296 "Use STM32F3/STM32G4 CCM SRAM" which has many details on the topic. The app note does not cover VS Code Extension however, so there may be subtile differences in the linker files, startup code etc. and you may have to tweak those.

hth

KnarfB