STM32H563 / H573 Dual-Single SPI as a double write only master

[RustleOfCicadaTHS]

Hi Experts,

Is it possible to use STM32H5 OctoSPI interface (configured as Dual-Single-SPI) as two individual transmit-only SPI masters?

Requirements:
1. Two devices connected to MCU are identical but receive different data
2. Devices are not a memory
3. No data needs to be received by MCU
4. No simultaneous write is required (edit after first reply: Simultaneous write is required)

If such configuration is possible, how will HAL code look like?
Which of OCTOSPI_IO0, IO1, IO2, IO3 pins are can be configured as 'MOSI'? 

Edit: I realized 'Dual SPI' and 'Dual-Single SPI' are a different things. Changed post subject to 'Dual-Single SPI'

[KDJEM.1]

Hello @RustleOfCicadaTHS and welcome to the Community :),

I think you want two connect two devices with only OCTOSPI interface using single-SPI mode.

There are 2 possible solutions to do that

• Solution1: Use a dedicated bit in OCTOSPI_CR register for external memory selection: MSEL bit. The idea is to select the external device to be addressed in single-, dual-, quad-SPI mode in single-memory configuration.
  MSEL:
  0: External memory 1 selected (data exchanged over IO[3:0])
  1: External memory 2 selected (data exchanged over IO[7:4])
  In this case, the IO0 and IO4 (SO) are in output mode will be used to output the data from STM32, then it are MOSI (master Output Salve Input).

• Solution2: Use different chip select GPIO pins for each device The two device must be connected to the same OCTOSPI instance, then the chip select of each device must be connected to an OCTOSPI chip select GPIO pin as shown in the below figure. The software should configure the chip select GPIO pin for the memory to be accessed by driving the GPIO configuration. For example, when transferring data to device 1, it is recommended to set the device 2 chip select pin (Pin2) to high voltage by using a pull-up resistor. In this case, the GPIO Pin2 is configured as GPIO Output "Pull-up" and the Pin1 is configured as Alternate Function.
  The IO0 (SO) is in output mode will be used to output the data from STM32, then it is MOSI (master Output Salve Input).

Notes:  

• These two proposed solutions can be applied when using identical or different SPI devices. In case of two different devices, before switching from device to another, it is recommended to reconfigure the OCTOSPI interface accordingly the desired device specification.
• Please wait for data transmission to be completed before switching from device to another.
• With STM32CubeMx toolchain, you are able to configure only one device. For that, I recommend you to code this behavior manually.

Is my reply answer you request?

Thank you.

Kaouthar

[RustleOfCicadaTHS]

Hi @KDJEM.1 , thanks for the reply.

> I think you want two connect two devices with only OCTOSPI interface using single-SPI mode.
Actually yes, use of single-SPI would satisfy my requirements based on Solution2 you provided - thus I believe my hardware will still be usable anyways.

However, Solution1 is closer to what I had in mind. It's good to know that Memory can be selected using a register. Question1: Does Memory selection work at runtime without time consuming OctoSPI peripherial reconfiguration? (assuming two identical devices).

I've researched the topic a bit further and found Dual-Flash configuration in AN4760 (Figure 13 and Table 9).
I believe that Dual-Flash = (Dual-Single or Dual-Dual or Dual-Quad) SPI that can be selected in CubeMX.
Based on this forum post you've previously anwsered I have a following question:
Question2: What if we wanted to write to both devices simultaneously using Dual-Flash (Dual-Single) SPI configuration? (assuming that data buffers for devices 1 & 2 were interleaved ahead of time, e.g.: [Byte1Dev1] [Byte1Dev2] [Byte2Dev1] [Byte2Dev2] )

Question3: Is it possible to mirror SPI CLK signal on additional pin to eliminate star connection (trace split in two) on PCB?

[tjaekel]

Q3: no, it is not possible to bring out the same SCK signal also on a different pin (just one or the other). I do not know what would happen if you configure two different pins with the "same" ALT to provide the same SCK output (interesting trial). I assume, MCU will take the last pin you have configured via ALT as QSPI SCK out.

You could use QSPI in order to send - in parallel - to two different chips. But just Tx (only MOSI used), Rx is not possible.

Based on your schematics: you would run QSPI in 4-lane-mode (real QSPI): on DIOx (e.g. bit 0) goes to one chip, the other DIOx (e.g. bit 2) goes to another chip. Both chips are selected at the same time (via NSS).

But: there is just one register for the CMD, ADDR, ALT, DATA sent via QSPI. You had to place the bits for each chip on the right bit position in the data word sent. You do not have two separate registers for each chip, just one for both and you have to merge the different bits into one register word. (effort, but possible).

If you do not need to write both chips really in parallel - you can use TWO separate NSS signals: select one chip, send, select the other chip and send. NSS can be also a regular GPIO signal (and use SW control for NSS).

Just to clarify some terms for better understanding how this QSPI device works in MCU:

• Single-SPI: it uses just DIO0 for MOSI (on a WRITE) and DIO1 as MISO (on a READ, not used here).
• Dual-QSPI: it uses two QSPI chips:
  a) with two NSS signals, to select one or the other or both at the same time
  b) upper bits on OCTAL-SPI (DIO4..DIO7), so as an 8bit SPI
• 
  So, Single-SPI uses just MOSI and DIO0 in your case.
• Dual-Single-SPI: I would assume: both as Single SPI (DIO0 only, maybe DIO1 for MISO, READ), but what about the NSS signal?
  a) not sure, if two NSS signals used now, are active at the same time (for a WRITE possible, but not for a READ)
  b) not sure, if now DIO4 is used also as Single-SPI but on the "upper" part (with two external chips), and just one NSS signal

Just configure the QSPI as you intent to use, use an oscilloscope and check if you get the signals as needed. Just to verify that the correct SPI transaction is generated (you do not need any external chip when doing just WRITEs).

BTW: why do you use QSPI (or OCTAL-SPI) device for it? Any regular SPI would do the same job.
QSPI device is a bit more complex in terms of config and use, e.g.: QSPI requires to setup a CMD, ADDR, ALT word before the DATA will be sent.
OCTAL or QUAD-SPI is intended for external memory devices whereas SPI is for any chip (also sensor chips and even SD Cards).

Remark: the STM32 OCTAL-SPI (or QUAD-SPI) is not really similar to a regular SPI. "Single-SPI" is not the same as on "regular" SPI (half-duplex vs. full-duplex, but you need just Tx/WRITE, OK anyway).

What is your intention?
a) two external chips written in sync, at the same time, but with different data (different MOSI)?
    One NSS selecting both at the same time?
b) two external chips, with Tx-only SPI (Master, Tx-only), but you can select one and then the other?
    (write both chips in a sequence)?
    Two NSS and selecting one or the other?

a) works only with DUAL or QUAD-SPI mode and bit-manipulations in the data register (and CMD, ADDR, ALT registers)

b) works on regular SPI, or on OCTAL-SPI in "Single-SPI" mode, but with two NSS signals (you might handle as SW GPIO NSS signals)