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Explorer II
August 30, 2023
Solved

STM32H563 SPI

  • August 30, 2023
  • 1 reply
  • 2745 views

Hi,

I could use some help getting started with SPI5 (limited feature set). I want to operate as SPI master and send a single byte. I want to control SS manually as ordinary GPIO out.

I've enabled the peripheral clock, and I can see in the debugger that FIFO flag TXTF goes high when I write to TXDR, and that I set CSTART. But nothing comes on MOSI or SCK, and EOT is never set.

Do you spot anything obvious in the code below?

What puzzles me is that if I set SSIOP = 0 and use the same code, TXTF and CSTART is not set. SSIOP should not be of importance when the peripheral is not in control of SS, right?

 

// Enable AF on MOSI, MISO, SCK. Set CS 1 and 2 as outputs (manual control).

GPIOF->MODER = (GPIOF->MODER & 0b11111111111100000011110000111111) | 0b00000000000010101000000101000000;

SPI5->CFG1 = 0b01110000000000000000000000000000;

SPI5->CFG2 = 0b10010001010000000000000000000000;

SPI5->CR2 = 1;

SPI5->CR1 = BIT(0);

 

SPI5->IFCR |= BIT(3); // Clear EOT flag.

SPI5->TXDR = data; // Load FIFO.

 

SPI5->CR1 |= BIT(9); // Transfer start.

 

// Wait for EOT.

while ((SPI5->SR & BIT(3)) == 0)

;

    This topic has been closed for replies.
    Best answer by Dimlite

    I solved it.

    With the two lines below missing, the MCU got stuck waiting for an EOT that never came.

    // Select AF5 (SPI MOSI, MISO and SCK) on PORTF[9:7]
    GPIOF->AFR[0] |= 0x50000000;
    GPIOF->AFR[1] |= 0x00000055;

    I would have expected nothing to show up on the I/O-pins, but not the actual register writing and reading to be affected. Oh well, assumption is the mother of all **bleep** ups :)

    Attached is the working code.

    1 reply

    DimliteAuthorAnswer
    Explorer II
    September 4, 2023

    I solved it.

    With the two lines below missing, the MCU got stuck waiting for an EOT that never came.

    // Select AF5 (SPI MOSI, MISO and SCK) on PORTF[9:7]
    GPIOF->AFR[0] |= 0x50000000;
    GPIOF->AFR[1] |= 0x00000055;

    I would have expected nothing to show up on the I/O-pins, but not the actual register writing and reading to be affected. Oh well, assumption is the mother of all **bleep** ups :)

    Attached is the working code.

    Graduate II
    September 4, 2023

    Good job :flexed_biceps:

    Mark your answer as best answer to be diffused to everyone.

    Best regards.

    II