STM32H573 Ethernet MII clocks

[microcoder]

Greetings,

I am using STM32CubeIDE version 1.18, Running FreeRTOS, and using the HAL

library to configure the ETH device.

 

I have the STM32H573 ETH port configured as MII, and communicating with an external

ethernet switch device (also in MII mode). We want the link to be Full Duplex 10 Mbps.

We can see that the MAC CR register has bit 14 as a zero, which is 10 Mbps mode.

 

GRISHKA $ peek 0x40028000

[40028000] 0x3830A003

 

Yet, we I probe the RX and TX clocks with my scope, I see both clocks at 25 Mhz (40 nsec period).

I believe at 10 Mbps, the clock frequency should be 2.5 Mhz (400 nsec period) ?

Thanks

Ken Carlson

Edit by ST Moderator: Add the right labels

 

[STackPointer64]

Hello,

Although you are using MII mode in your configuration, the PHY integrated with the STM32H573, specifically the LAN8742A/LAN8742Ai, communicates with the MCU via a standard RMII interface and is clocked using a 25 MHz crystal oscillator according to the datasheet. In your case, the 100 Mb/s-MII mode was selected by the auto-negotiation process between the two boards, which explains the 25 MHz clock signal you observe on your scope.

As shown in the PHY block diagram, the LAN8742A/LAN8742Ai supports communication with the Ethernet MAC through RMII, providing full-duplex 10BASE-T/100BASE-TX operation at 10 Mbps and 100 Mbps speeds.

• LAN8742A/LAN8742Ai Datasheet

EDIT: Added more details for further clarity

Best regards,

[microcoder]

Thank you for the quick and informational response!

I tried putting our external device in 100 Mbps MII, but it still drops

transmit packets, must be something else, maybe flow control?

Anyways, thanks for the assistance!

Ken

 

[STackPointer64]

What I suggest you do is try the following steps:

• Run your application in debug mode and set a breakpoint inside the LAN8742_GetLinkState function. Check the value returned by the function, whether auto-negotiation is enabled, and the selected speed and duplex mode. During debugging, try forcing the external device to a specific speed and verify if the STM32 side matches that speed.

• Regarding the dropped transmit packets, this could be related to flow control. To investigate, please refer to this article, which explains how to monitor the number of frames detected and received, as well as the flags triggered in case of errors.

Debugging tips when working with an Ethernet peripheral 

[microcoder]

Thanks! 

I am running FreeRTOS, I only see the LAN8742_GetLinkState source code in the AzureRTOS (ThreadX) software.

 

Ken

 

[STackPointer64]

You’re most welcome!

The function is located in lan8742.c under Drivers\Components\lan8742\. Please navigate there and set a breakpoint at line 264. Then, debug your code and step through it slowly until you observe which speed and duplex mode are chosen. Make sure to perform this while your board is connected to the external device and conduct the tests I suggested earlier.

[STackPointer64]

Hello @microcoder,

Do you have any updates regarding your problem? Were you able to resolve it?

Best regards,

[microcoder]

Internal

Hi,
No, the problem is not yet solved. ☹
Thanks
Ken

[STackPointer64]

Hello,

Could you please provide me with the current status of the issue? This will help me guide you more effectively.

Best regards,

[microcoder]

Internal

Hi,

Here is the issue.

STM32H5723 connected to KSJ8995 ethernet switch IC over MII bus (not RMII).
The STM32 is the MII bus master (generates both the RX and Tx clock).

The two MAC/Phy endpoints of the MII bus are configured as 10 Mbps, auto-negotiate disabled,
full duplex. The link comes up on both sides.

Our two working configurations, where packets do not get dropped by the ethernet switch are:

1) RCC HSI clock, divide by 2, divide by 1, for a 32 MHz FCLK processor clock, ETH at 64 MHz
2) RCC HSI clock, divide by 1, divide by 1, for a 64 MHz FCLK processor clock, ETH at 64 MHz

If we change the RCC to the HSE external clock, to either one of the two non-working configurations, 3 and 4
below, the switch drops packets with Ethernet Rx CRC errors, Rx alignment errors, or Rx Jabber errors.

The packets are being sent from the STM32 over then MII, to the switch, and are being
dropped right at the switch's RX MII interface. Rate and packet size do not matter, 64 byte
packets at 1 PPS still get dropped.

3) RCC HSE (crystal oscillator at 25MHz), 125 MHz FCLK processor clock, ETH at 62.5 MHz
4) RCC HSE (crystal oscillator at 25MHz), 62.5 MHz FCLK processor clock, ETH at 62.5 MHz
Once I saw, and asked about, the 25 Mhz clock being generated by the STM32, I changed
both sides to 100 Mbps, auto-negotiate disabled, and full duplex, and packets still
work with 1) and 2), but still fail with 3) and 4)?

I am wondering of the 62.5 MHz ethernet peripheral clock is valid?

I have not had time to play with the flow control configuration yet, but will.

Thanks for reaching out!

Ken Carlson
Draeger MSI

[STackPointer64]

Hello @microcoder ,

Thank you for your patience. After researching the issue and testing your configuration, I found that the PLL clock output must be between 128 MHz and 560 MHz, as specified in DS14121. In your setup, the 25 MHz HSE divided by 2 (PLLM) gives 12.5 MHz, multiplied by 10 (N) equals 125 MHz, and divided by 2 (PLLQ) results in 62.5 MHz.

This 125 MHz PLL clock does not meet the minimum required frequency.

To resolve this, please try increasing the multiplier (N) to at least 11 to meet the minimum clock requirement. Let me know how it goes.

Best regards,