STM32H573 I2S audio clock problem
Hi,
I'm trying to set the following parameters for I2S in Device Configuration Tool (STM32CubeIDE v1.14.0):
- Master Clock Output enable
- audio frequency: 48kHz
- Data and Frame Format: 16 bits
I want to connect an external 12.288 MHz clock to the AUDIOCLK input, but I get the following message:
"With this I2S Clock (12.288 MHz), the divider value (0) is too low to obtain the desired Audio Frequency (48.0 kHz). The I2S Clock must be higher than (43.008 MHz)."
The problem is that according to RM0481, the I2SDIV may have the value 0:
"I2SDIV can take any values except the value 1, when ODD is also equal to 1".
A similar problem was described here:
however, in that case in RM0090 the value 0 and 1 were actually forbidden for the STM32F429 in the I2SDIV field. For STM32H573 such values are allowed:
"CHLEN and ODD can be either 0 or 1. I2SDIV can take any values from 0 to 255 when ODD = 0, but when ODD = 1, the value I2SDIV = 1 is not allowed. When I2SDIV = 0, then {(2 x I2SDIV) + ODD} is forced to 1."
Is this a CubeMX/STM32CubeIDE bug or do I really need to use a higher clock rate on the AUDIOCLK input?
