STM32H573 SDMMC NEGEDGE valid/hold time

[benjacam]

Dear ST Community,

I am using the STM32H573's SDMMC interface to communicate with a soft eMMC device implemented in FPGA:

• 1.8V I/O
• DDR==0 mode
• CLKDIV>0.

I'm setting up the timing constraints for the FPGA's CMD input versus the CK input and I have a query about the SDMMC interface timing.

In the datasheet, Table 123 defines the tov and toh parameters. In which mode are these parameters valid? CLKDIV>0 and NEGEDGE==0?

How would NEGEDGE==1 change tov and toh? Based on the diagrams of figure 164, I believe the tov and toh would increase by 1/2 the clock period. Is that correct?

Thank you. Ben