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Visitor II
December 2, 2024
Question

STM32H7 Dual Core MCU CM4 FLASH 0x081E0000

  • December 2, 2024
  • 1 reply
  • 1714 views

Hello ,
I am working with stm32h747.

M4 .ld File

FLASH (rx) : ORIGIN = 0x08100000, LENGTH = 1024K

M7 .ld File

FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K

With the above settings I can run Core M7 and M4 properly.
I need more flash on the m7 side and I want to separate the flash as follows

M4 .ld File

FLASH (rx) : ORIGIN = 0x081E0000, LENGTH = 128K

M7 .ld File

FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1896K
I also make adjustments with cube programer as in the picture.b.pnga.png

Core m7 works but m4 doesn't seem to work.I think I'm missing something or doing something wrong. Can you help me?
Codes are as follows

CM4 Main  Code : 

int main(void)
{
 MPU_Config();
 __HAL_RCC_HSEM_CLK_ENABLE();
 HAL_HSEM_ActivateNotification(__HAL_HSEM_SEMID_TO_MASK(HSEM_ID_0));
 HAL_PWREx_ClearPendingEvent();
 HAL_PWREx_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFE, PWR_D2_DOMAIN);
 __HAL_HSEM_CLEAR_FLAG(__HAL_HSEM_SEMID_TO_MASK(HSEM_ID_0));

 HAL_Init();
 MX_MDMA_Init();
 MX_DMA_Init();
 MX_GPIO_Init();
 MX_SPI1_Init();
 while (1)
 {
 HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_13);
 HAL_Delay(100);
 }
}
​

CM7 Main  Code :
int main(void)
{

 int32_t timeout;
 MPU_Config();
 SCB_EnableICache();
 SCB_EnableDCache();
 timeout = 0xFFFF;
 while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) == RESET) && (timeout-- > 0));

 HAL_Init();
 SystemClock_Config();
 PeriphCommonClock_Config();
__HAL_RCC_HSEM_CLK_ENABLE();
HAL_HSEM_FastTake(HSEM_ID_0);
HAL_HSEM_Release(HSEM_ID_0,0);
timeout = 0xFFFF;
while((__HAL_RCC_GET_FLAG(RCC_FLAG_D2CKRDY) == RESET) && (timeout-- > 0));
if ( timeout < 0 )
{
Error_Handler();
}


 MX_GPIO_Init();
 while (1)
 {
 HAL_GPIO_TogglePin(GPIOC, GPIO_PIN_1);
 HAL_Delay(100);
 }
}
    This topic has been closed for replies.

    1 reply

    Technical Moderator
    December 2, 2024

    Hello,

    First in next time, please use </> button to paste your code.

    Second,

    Don't modify option bytes. Keep the default boot address:

    SofLit_0-1733148758284.png

    Just use the linker file as you did:

    FLASH (rx) : ORIGIN = 0x081E0000, LENGTH = 128K

     I'm editing your post then. 

    snnzdmr1Author
    Visitor II
    December 3, 2024

    Okay, I'll use this for the code area now.(</>)
    As you said, I only changed the CM4 .ld file. The code 0x081e0000 is loaded to this address. I can verify this with cube programer. I do not change the Option bytes. Default boot address(0x08100000 ). But still CM4 is not working.


    Technical Moderator
    December 3, 2024

    @snnzdmr1 wrote:

     I do not change the Option bytes. Default boot address(0x08100000 ). But still CM4 is not working.


    Sorry, this is not the default option byte value for boot address and I think 'e' in 0x081E0000 came from your configuration:

    SofLit_0-1733215235055.png

    From the RM. The factory value is 0x0810 while you have 0x081e.

    SofLit_1-1733215476143.png

     

     

    Technical Moderator
    December 3, 2024

    Project upated with an updated CM7 linker file:

     FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1920K

    2048K - 128K = 1920K

    snnzdmr1Author
    Visitor II
    December 4, 2024

    Unfortunately I don't have  to NUCLEO-H745 try this code.

    You tried it and if it works I will focus on finding my own mistake.  Thank you very much for your detailed help.

    Graduate II
    December 4, 2024

    I think you can also get the CM7 to start the CM4 side.

    Or create a unified image, where say the startup code can detect which core it's running on, and fork to the code/vector space each uses, with the SystemInit() code then establishing where the SCB->VTOR lives.

    ST has an annoying habit of using #defines for this independently of the Linker Script, but you can use symbols, ie g_pfnVectors to establish this on-the-fly. Look at your SystemInit() code in system_stm32xyz.c