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Visitor II
March 23, 2025
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STM32H7 - MPU Configuration

  • March 23, 2025
  • 1 reply
  • 910 views

Hi All, 

I was testing my new STM32H746XIH6 board and met the post below by @GSpre.1 during a search about SDRAM  performance. 

GSpre.1 - Performance characteristics of SDRAM on STM32F7508-DISCO board 

I don't have a lot of time to read MPU documentation, maybe someone has an idea about the code piece below that @GSpre.1  adviced. 

 

I did not perform a precise measurement but used Systick for both internal and external (32-bit SDRAM) memory array manipulation time for the same data length. (I-Cache and D-Cache are both enabled as expected.)

Internal memory test:  12ms 

External memory test: 47ms without the code below  

External memory test: 13ms.with the code below

 

* What exactly the code below does ? 

* Am I compromising from anything for speed ? 

 

There are a lot of job to do during board bring-up I have no time to read a lot of documentation. I will be appreciated if someone share experience...

BTW, thanks for sharing @GSpre.1

Regars. 

 

 MPU_Region_InitTypeDef MPU_InitStruct;
 HAL_MPU_Disable();
 MPU_InitStruct.Enable = MPU_REGION_ENABLE;
 MPU_InitStruct.BaseAddress = 0xD0000000;
 MPU_InitStruct.Size = MPU_REGION_SIZE_32MB;
 MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS;
 MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE;
 MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE;
 MPU_InitStruct.IsShareable = MPU_ACCESS_NOT_SHAREABLE;
 MPU_InitStruct.Number = MPU_REGION_NUMBER0;
 MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL1;
 MPU_InitStruct.SubRegionDisable = 0x00;
 MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE;
 HAL_MPU_ConfigRegion(&MPU_InitStruct);
 HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT);

 

    This topic has been closed for replies.
    Best answer by mƎALLEm

    Hello,

    The address 0xDXXX XXXX is not a cacheable region by default. Device means not cacheable even the caches are enabled (data and instruction).

    mALLEm_0-1742740114256.png

    The code you shared makes the 0xDXXX XXXX region cacheable.

    So the results you shared are expected.

    Hope that helps

    1 reply

    mƎALLEmAnswer
    Technical Moderator
    March 23, 2025

    Hello,

    The address 0xDXXX XXXX is not a cacheable region by default. Device means not cacheable even the caches are enabled (data and instruction).

    mALLEm_0-1742740114256.png

    The code you shared makes the 0xDXXX XXXX region cacheable.

    So the results you shared are expected.

    Hope that helps

    March 23, 2025

    Dear @mƎALLEm ,

    I thank you for your prompt response, especially on Sunday :) 

    Regards.