STM32H7 PSSI discrepancy between Datasheet and ref.manual

[Michal Dudka]

Hi,
Ref.manual (RM0477 Rev 8) in chapter 32.3.3 PSSI clock says

In case when PSSI transmitting data, then RDY pin is input.
Datasheet (DS14360 Rev 2) shows setup and hold time of RDY pin (input) referenced to rising edge as well as data pins (outputs).



I think that's a contradiction. So how is it really and to which edge do RDY setup and hold times relate ?
Thanks,
Michal Dudka

[KDJEM.1]

Hello @Michal Dudka,

 

Thank you for bringing this issue to our attention.

I will check internally this issue between the reference manual and datasheet. And, I will come back to you with details as soon as possible.

Internal ticket number: 201823 (This is an internal tracking number and is not accessible or usable by customers).

 

Thank you.

Kaouthar

[mƎALLEm]

Hello,

Do you mean the description in the reference manual is inverted? and should be:

When CKPOL = 0
– Input pins are sampled on PSSI_PDCK rising edge
– Output pins are driven on PSSI_PDCK rising edge
• When CKPOL = 1
– Input pins are sampled on PSSI_PDCK falling edge
– Output pins are driven on PSSI_PDCK falling edge

[Michal Dudka]

As I understand the timing diagram, that's how it should be. But naturally I have no idea which information is correct one. And the way to find it out is somewhat difficult (I would have to sweep the input signal and verify on the STM side when it interpreted it correctly)

 

[Michal Dudka]

- deleted

[Michal Dudka]

I had no choice but to test it. I've generated 16MHz clock from lab generator as source for CLK input. On second channel i've generated 20ns pulze connected to RDY input. Then i've changed RDY pulse phase shift respect to CLK to check if RDY is read on rising or falling edge. And the results with CKPOL=0 are:
- outputs are driven at rising edge
- inputs are sampled on falling edge
The Reference manual is right and Datasheet is misleading. In other words, setup and hold times are plotted related to rising edge (with CKPOL=0), but should be plotted related to falling edge.

From my point of view it is documentation bug. 

[KDJEM.1]

Hello @Michal Dudka,

 

After checking, there is an error in the PSSI transmit timing diagram of datasheet.

The RDY signal is sample half cycle before the launch to the data.

This issue will be fixed in the coming datasheet revision.

Thank you for your contribution in community.

Kaouthar

[Michal Dudka]

Hi @KDJEM.1 
I'm glad to hear that it will be fixed. What about this, much more serious, issue ?
https://community.st.com/t5/stm32-mcus-products/stm32h7r3-pssi-rdy-de-bug/td-p/766737
PSSI obviously transmit data even with deasserted DE signal under well-documented conditions.
I put a lot of work into extracting it into a clear format (because it was key to my application) and anyone who uses PSSI with flow control (DE+RDY) will spend many hours searching for it.