STM32H7 QSPI & MDMA data split into 4bit packets

[regjoe]

Hello,

I configured QSPI and MDMA in CubeMx and generated the initialization code. I merged the flash demo code (QSPI_ReadWriteDual_DMA), available for the H743 evaluation board, into my project.

Regarding the QSPI waveform I'm puzzled whats going on during the flash read and programming sequence. This is the QSPI transmit / flash program (command 0x32) waveform:

This is the QSPI receive / flash page read (command 0x6b) waveform:

In my understanding the command/address/dummy bytes are sent as expected.

But then the following data is split into 4 bit chunks during transmit and 8 bit chunks during receive. I have no clue why and which parameter is to blame here.

Here is the initialization code. H753 clock is 400MHz, QSPI clock is 40MHz.

 

 

 

hqspi.Instance = QUADSPI;
hqspi.Init.ClockPrescaler = 4;
hqspi.Init.FifoThreshold = 1;
hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
hqspi.Init.FlashSize = 24;
hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE;
hqspi.Init.ClockMode = QSPI_CLOCK_MODE_0;
hqspi.Init.DualFlash = QSPI_DUALFLASH_ENABLE;
hqspi.Init.FlashID = QSPI_FLASH_ID_2;
 
hmdma_quadspi_fifo_th.Instance = MDMA_Channel1;
hmdma_quadspi_fifo_th.Init.Request = MDMA_REQUEST_QUADSPI_FIFO_TH;
hmdma_quadspi_fifo_th.Init.TransferTriggerMode = MDMA_BUFFER_TRANSFER;
hmdma_quadspi_fifo_th.Init.Priority = MDMA_PRIORITY_HIGH;
hmdma_quadspi_fifo_th.Init.Endianness = MDMA_LITTLE_ENDIANNESS_PRESERVE;
hmdma_quadspi_fifo_th.Init.SourceInc = MDMA_SRC_INC_BYTE;
hmdma_quadspi_fifo_th.Init.DestinationInc = MDMA_DEST_INC_DISABLE;
hmdma_quadspi_fifo_th.Init.SourceDataSize = MDMA_SRC_DATASIZE_BYTE;
hmdma_quadspi_fifo_th.Init.DestDataSize = MDMA_DEST_DATASIZE_BYTE;
hmdma_quadspi_fifo_th.Init.DataAlignment = MDMA_DATAALIGN_PACKENABLE;
hmdma_quadspi_fifo_th.Init.BufferTransferLength = 1;
hmdma_quadspi_fifo_th.Init.SourceBurst = MDMA_SOURCE_BURST_SINGLE;
hmdma_quadspi_fifo_th.Init.DestBurst = MDMA_DEST_BURST_SINGLE;
hmdma_quadspi_fifo_th.Init.SourceBlockAddressOffset = 0;
hmdma_quadspi_fifo_th.Init.DestBlockAddressOffset = 0;

 

For DMA transmit/receive these HAL functions are used in the demo:

HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)

Looks to me the DMA is not fast enough to feed the QSPI?

BTW: In most SPI demo DMA is used but QSPI is using MDMA. Why?

 

 

[Tesla DeLorean]

>>In most SPI demo DMA is used but QSPI is using MDMA. Why?

Usually a function of which bus the peripherals on, and the bus-matrix furnishing connectivity between memory and peripheral. I'm sure there's a diagram in the RM

[regjoe]

Hi @Tesla DeLorean 

I see that the data paths differ. But does this have any impact on how to use DMA and MDMA? E.g. regarding the data cache handling?

For SPI/DMA the transmit/receive buffers are aligned and buffers must be cleaned/invalidated. For QSPI/MDMA this seems not necessary, telling from the evaluation board demo.

Second, for SPI transmit/receive I have to configure 2 DMAs, one for transmit and one for receive. For MDMA there is only 1 channel required. How does this work?

In CubeMx there is an extra tab in the MDMA configuration page. Why? Just a little helper to configure the QSPI DMA with appropriate values or is this a "special" MDMA channel used for QSPI?

[regjoe]

I ran the unmodified QSPI_ReadWriteDual_DMA on a STM32H753_EVAL2 board and got exactly the same results.

During

HAL_QSPI_Transmit_DMA

the SPI clock is paused after 4 or 8 bits if the SPI clock is higher than ca. 25MHz.

So this seems to be related to the H7 e.g. the QSPI, MDMA, MPU or cache stuff.

Any idea in which direction to go?