STM32H7 QUAD SPI DDR timing

[regjoe]

Hello,

I have a STM32H75x design and suffer from read errors in DDR timing, no matter if run at 50MHz or slower.

It seems that the data hold time of 1ns the H7 is violated. The data output hold time of the SPI NOR MX25L12845 flash is 1ns, which seems to be too short for H7. Due to the fact, that the clock edge takes also ca. 0.5-1ns, the timing should be safe in my opinion. Nevertheless, a read failure arises if the drive strength of the flash is lower than 45Ohm and GPIO pin speed is higher than MEDIUM.

The H7 evaluation boards are equipped with Micron flash with 1.5ns and it seems that this value is fine for H7.

Therefore I doubt the data input hold time of 1ns@3.3V in table 181:

In my opion, this value should be longer than 1ns. Any user experience?

Thank you,

Jochen

 

[KDJEM.1]

Hello @regjoe;

 

I have a STM32H75x design and suffer from read errors in DDR timing

Are you activating the delay block?

For DDR mode, please make sure that DHHC bit set (RM0433).

 

Thank you.

Kaouthar

[regjoe]

Hello @KDJEM.1 ,

no, it isn't activated. If activated the write fails. As I understand, DHHC affects H7 write operation timing, but I suffer from H7 read error.

I should have mentioned that MX66L1G works fine on my HW, no matter which H7 GPIO speed is set (MEDIUM, HIGH, VERY HIGH) and flash driver strength (90-15 Ohm).

The MX25L128 fails on all 4 boards tested if flash drive strength is set to 30 Ohm. If set to 15 Ohm, even the auto status byte polling fails on write enable set command. I can watch the correct data on the scope but the H7 seems to recognize an incorrect bit pattern. Seems the high drive strength causes the H7 to fail. 

Seem like there is kind of timing incompatibility between the H75x and MX25L128 but I cannot find a difference in the flash data sheets to blame for.

 

MX66L:

MX25L:

 

ODS(0,0) = 30 Ohm results in flash memory read error.

ODS(1.1) = 15 Ohm results in status register read error.

The calculated inductivity load is about 10pF.

The flash output hold time is on both flash 1ns but I guess that the value for MX25 is shorter than for the MX66.  

 

 

 

[regjoe]

Did some tests yesterday and observed a strange behaviour, maybe the key to the status register auto-polling failure as already observed here Solved: STM32H753 QSPI Status Flag Polling fails with Inst... - STMicroelectronics Community

If the MX25 flash driver strength is kept to default 30Ohm, the polling is successful and timing looks like this:

Note the strange timing of the H7 in the first 2 clocks of the command phase.

If set to 15Ohm (highest driver strength), the timing looks like this:

Note the strange behaviour of IO3 and IO2 in clock period 2.

This does to appear on MX66 at 15 Ohm setting, too, but less effect:

At higher drive strength, the signals on IO2/3 are clamped. I cannot find this effect on IO0/1. Maybe this is a result of the special functions WP# / RESET# of pins IO2/3?

Second I noticed that the clock edge to data output valid delay is ca. 0.7ns shorter on MX25 than MX66, although in the specification both have the same value.