STM32H7 QUADSPI clock configuration

[nonoriri]

I have question about STM32H7 QUADSPI clock configuration.

It seems STM32H7 contains two different source clocks.

If I select HCLK3 as the clock source for the QUADSPI Clock Mux, how is the QUADSPI clock frequency calculated? Regardless of selecting HCLK3, will the QUADSPI clock still be calculated as PLL1Q / (Prescaler + 1)?

[LCE]

I think the upper picture is wrong, instead of HCLK it should be:

quadspi_ker_clk -> prescaler -> QSPI_CLK

So what you select with the QSPI clock mux in the lower picture is actually (or should be) quadspi_ker_clk as input to the prescaler.

HCLK is always the interface clock between MCU and the QSPI peripheral.

So if you select HCLK3 then this goes to the QSPI clock prescaler - why should it be PLL1Q?

Inconsistency and minor errors in documentation concerning clock naming is a known ST issue...

[nonoriri]

Thank you very much for the answer.

I believe that if I select HCLK3, the QSPI clock is HCLK3 / (Prescaler + 1).

If I select PLL1Q, the QSPI clock is PLL1Q / (Prescaler + 1).

 

I wonder why the documentation states the following sentence:

quadspi_hclk (hclk3)
It is the source clock for the register interface. This clock has no impact on the QUADSPI CLK.

[LCE]

> quadspi_hclk (hclk3)
> It is the source clock for the register interface. This clock has no impact on the QUADSPI CLK.

They should have added:

"Unless it is selected as source for QUADSPI CLK in the QSPI clock mux"