STM32H723: Window WatchDog (WWDG)

[jowakar122]

I am using STM32H723 and have implemented WWDG. Below is my configuration: 

Are there possibility that when the system resets due to watchdog it would not trigger its ISR. 

[LCE]

Not sure, never used WWDG, but why not 

NVIC_DisableIRQ(WWDG_IRQn);

?

[TDK]

The EWI interrupt will function as intended.

There exist scenarios in which it will not be called. For example, if interrupts are disabled, it won't be called.

[jowakar122]

@TDK I am not disabling its interrupts. Even if I disable the interrupt it will still reset but without triggering its ISR

[LCE]

> Are there possibility that when the system resets due to watchdog it would not trigger its ISR.

...

> Even if I disable the interrupt it will still reset but without triggering its ISR

 

Isn't that what you asked for? Scratch head...

[jowakar122]

I had a doubt about RTOS blocking the WWDG ISR. So I have implemented without RTOS and the issue persists. 

int main(void)
{

 /* USER CODE BEGIN 1 */

 /* USER CODE END 1 */

 /* MPU Configuration--------------------------------------------------------*/
 MPU_Config();

 /* Enable the CPU Cache */

 /* Enable I-Cache---------------------------------------------------------*/
 SCB_EnableICache();

 /* Enable D-Cache---------------------------------------------------------*/
 SCB_EnableDCache();

 /* MCU Configuration--------------------------------------------------------*/

 /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
 HAL_Init();

 /* USER CODE BEGIN Init */

 /* USER CODE END Init */

 /* Configure the system clock */
 SystemClock_Config();

 /* USER CODE BEGIN SysInit */

 /* USER CODE END SysInit */

 /* Initialize all configured peripherals */
 MX_GPIO_Init();
 MX_USART3_UART_Init();
 MX_TIM24_Init();
 MX_LWIP_Init();
 MX_WWDG1_Init();
 /* USER CODE BEGIN 2 */
 HAL_UART_Transmit(&huart3, "OS Starts\n", 10, 10);
 /* USER CODE END 2 */

 /* Infinite loop */
 /* USER CODE BEGIN WHILE */
 while (1)
 {
	 HAL_WWDG_Refresh(&hwwdg1);
	 HAL_GPIO_TogglePin(GPIOB, LED_GREEN_Pin);
	 MX_LWIP_Process();
	 if(!FLAG_OTA)
	 {
		 if((FLAG_LINK) && (!FLAG_TCP_CONNECTED))
		 {
			 tcp_client_init();
		 }
	 }
	 else
	 {
		 if(!FLAG_TFTP_CON)
		 {
			 HAL_UART_Transmit(&huart3, "TFTP\n", 5, 5);
			 tftp_init_client();
//			 HAL_Delay(10);
		 }

		 if(FLAG_TFTP_CON) { if(!OACK_RECV) { send_rrq_periodic(); } }

		 if(Flag_TFTP_Error) { HAL_UART_Transmit(&huart3, "ERROR\n", 6, 5); /*NVIC_SystemReset();*/ }

		 if(Flag_FILE_RECVED)
		 {
			 uint32_t t_buf[1] = {tsize};
			 if(FLASH_If_Erase(ADDR_FLASH_SECTOR_7_BANK1, 1) == FLASHIF_OK)
			 {
				 if((FLASH_If_Write(ADDR_FLASH_SECTOR_7_BANK1, t_buf, 1)) != FLASHIF_OK)
				 {
					 strcpy(debug_string, "\r------>ERROR: Writing file size in flash<------\n");
					 HAL_UART_Transmit(&huart3, (uint8_t*)debug_string, strlen(debug_string), 10);
				 }
			 }
			 Flag_FILE_RECVED = 0;
//			 NVIC_SystemReset();
		 }
		}
		HAL_Delay(100);
 /* USER CODE END WHILE */

 /* USER CODE BEGIN 3 */

 }
 /* USER CODE END 3 */
}

This is what was printed in my log:

 

[jowakar122]

For now I am using a timer to refresh the WWDG when file transfer is happening and it is working fine. But couldn't figure out the reason behind the above mentioned unusual condition.