Skip to main content
Explorer II
May 24, 2024
Question

STM32H743 pwm interrupts with high frequency

  • May 24, 2024
  • 2 replies
  • 2131 views

Greetings!

I generate periodically a 10MHz PWM signal of 8 pulses. The PWM signal has high polarity so the first edge is falling. I need to generate an interrupt/event on the rising edge that'll signal DMA to move data from a GPIO IDR to a data buffer. So 8 interrupts/events that cause 8 DMA transfers. I have tried using one pulse mode with a repetition counter of 8 but either the pwm doesn't stop during the interrupt or it goes too fast and if I just generate one pulse with no repetition and use a counter in

 

HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef* htim){
		tim_irqs++;
		if(tim_irqs < 8){
			HAL_TIM_PWM_Start_IT(&htim15, TIM_CHANNEL_1);
		}
}

 

it generates only one pulse. Variable tim_irqs is declared as volatile. Not doing any of that DMA stuff yet, just been trying to get the interrupts working correctly. I've been thinking if this is an timing problem (program runs too slow) or is the timer configured incorrectly? But the CPU frequency is 480MHz and the timer frequency is 240MHz. This is the first time I'm using timers like this and honestly not 100% sure what I'm doing. Any help would be appreciated. I've attached screenshots of my Cube setup and clock configuration.

EDIT: Added the photos to the text body

image.png

image.png

    This topic has been closed for replies.

    2 replies

    PyryAuthor
    Explorer II
    May 24, 2024

    UPDATE: I got the counter working right when I switched to Output compare mode, but the timer still generates too many pulses

    IMG_20240524_160139222.jpg

    Explorer
    May 26, 2024

    Going into interrupt subroutine and back quite expensive in clk cycles. Having modern ~500MHz uCPU doesn't change situation much, since more advance uCPU demands even more time for breaking main loop(). Think like 1usec, so limits about 1 MHz at max. Reconsider your design completely on hardware approach, chaining two or three timers in sequance. 

    PyryAuthor
    Explorer II
    May 27, 2024

    Yea that's what I kinda feared. How would the timer chaining work in this situation? Would it be with input capture or something similar with one timer acting as a master and 3 as slaves? Also if I have understood correctly, DMA does not require any CPU intervention so in itself it would be doable with the 10 MHz frequency, just the triggering is the problem.

    PyryAuthor
    Explorer II
    May 27, 2024

    Thanks for this, although we decided to change our hardware and include an FPGA to handle the data and use the mcu just for control signals.