STM32H743 QSPI single mode can't receive data

[Jason927]

I'm using STM32H743VGT6 QSPI drive an AMOLED screen.

AMOLED read sequence need IO0 line send and receive data.(Picture 1)

But I checked the H743 Reference manual, it says in the single mode, IO0 just output, not input.(Picture 2)

How do I fix to make sure the IO0 data received?

 

 

[KDJEM.1]

Hello @Jason927 ;

 

As mentioned in reference manual RM0433 Rev8 section 23.3.4 QUADSPI signal interface protocol modes (Single-SPI mode): This legacy SPI mode allows just one single bit to be sent/received serially. In this mode, data are sent to the flash memory over the SO signal (whose I/O shared with IO0). Data received from the flash memory arrive via SI (whose I/O shared with IO1). The Hardware configuration for Single-SPI mode is shown in the below figure.

->AMOLED read sequence need IO0 line send and receive data

For this specially case, I think you need to configure the QUADSPI interface in Dual-SPI mode because  

In dual-SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.

So, IO0/IO1 are at high-impedance (input) during the data phase for read operations, and outputs in all other cases.

For more information about the Dual-SPI mode, I recommend you to look at RM0433 Rev8 section 23.3.4 QUADSPI signal interface protocol modes (Dual-SPI mode) and at AN4760 section 3.2.2 Dual-SPI mode.

In Dual-SPI mode the hardware configuration is similar to the one in single mode, but here two lines are used
for data, it means that data is sent and received in two lines.

I hope this help you.

Thank you.

Kaouthar

[Jason927]

Understood.   Is ST 's QSPI peripheral specialized for ext flash memory?

As you say, in Dual-SPI mode, I received data successfully, but I need discard some bits to make data in right place.Data not total processed by hardware.This op waste some cpu efficiency.

[KDJEM.1]

Hello @Jason927;

 

The QUADSPI/OCTOSPI/XSPI interfaces support all devices aligned with the command format and order mentioned in the STM32 reference. 

It is necessary to check the compatibility of the command format between the QUADSPI interface and the devices such as command order  (Instruction phase, Address phase, Alternate-byte phase, Dummy-cycle phase, Data phase) and the bytes number for each command.

 

Please look at Overall FAQs for QUADSPI/OCTOSPI/HSPI/XSPI.

 

If your initial request is answered please click on Accept as Solution on the reply which answered your question.

Thank you.

Kaouthar