STM32H745 - Code is sometimes slow, but can be fixed by NOP

[Kurngop32]

Hello,

I have a rather strange problem on the CM7, where code executes with half or third the speed it should.

I have no idea what is causing this, but I know how to fix it: by adding one or several NOPs somewhere in the code.

Example: an ISR is taking 10us to execute. I change something (seemingly) unrelated in the code, and suddenly this ISR, with the same code, takes 20us. Now I add a NOP at the beginning of the main, and the ISR takes 10us again.

Any ideas what the cause might be?

edit:
Some details:

• no cache used
• CM7 code is mostly RAM code on TCM
• build with -Ofast
• FMC addresses an FPGA (memory mapped registers)
• there are only two interrupts with same priority
• clocks are unchanged, because the ISR frequency stays the same.

[TDK]

Look at the disassembled interrupt code. Possibly an alignment issue. Possibly a misinterpretation of what's happening. How are you measuring it? Note that things are cached and things are often competing for the same resources. Writing to GPIO will not toggle the pin exactly when the instruction completes, though it shouldn't have a 10us lag either.

If you stop the main thread, does it change things?

Note that the CM7 core is complicated and instructions are not guaranteed to be a fixed number of cycles.

[Kurngop32]

I measured it with toggling IOs, with a counter in the main while loop, also with DWT. At one point the code got so slow the WDT was triggered, so it was definitely a noticeable decrease in speed.

(un)fortunately it does not happen right now, and I didn't save a bad version. I'll look at the disassembly the next time it happens.

 

[Pavel A.]

> At one point the code got so slow the WDT was triggered

Please consider the notorious speculative execution issue https://community.st.com/t5/stm32-mcus-products/speculative-access-and-stm32h7-memory-protection-unit/td-p/119039