STM32H750 issue switching system clock to PLL1

[_MaticBabnik]

I'm trying to get the STM32H750 discovery board running at 400MHz with as little code as possible. (plain C with ST's startup file, cherry-picking structs and defines from CMSIS)
As far as I can tell I do most of the things, ST's examples do before and in SystemClock_Config.
Using a debugger I checked the following registers just before switching the clock source to PLL1.

 

Register | ST's example | difference?

RCC
	CR			0303 7025 . 
	CIER		 		0	.
	CFGR		 		0	.
	D1CFGR		 48	.
	D2CFGR		 440	.
	D3CFGR		 40	.
	PLLCKSELR	 202 0052	dont have DIVM2 AND DIVM3;
	PLLCFGR		 1ff 0009	dont have PLL2,3 cfg
	PLL1DIVR	 103 029f	.
	PLL1FRACR	 		0	.
	AHB2ENR				0	.	
	AHB3ENR				0	.
	AHB4ENR		 0 	.	
	APB4ENR		 1 0002	.
SCB
	SHCSR				0	.
	CCR		 	 7 0210	no caches
PWR
	CR3		 500 0042	.
	D3CR		 e000 	.
	CSR1		 e000	.
SYSCFG
	CCCSR			 0	.
FLASH
	ACR		 37 .

 

 After the switch my code gets stuck waiting for PLL1 in SWS.
Any ideas why the clock doesn't switch? Could the lack of PLL2,3 config be the reason?

[AScha.3]

Why don't you use Cube / HAL, set clock tree and debug etc, generate code and then just look, how it's done. If you can do same better, then you still can try . But have a reference, how exactly your configuration can be initialized.