STM32H750 LPSDR @ 100Mhz

[James Panko]

Hi Team, 

Working on a custom design using STM32H750 and 2 Winbond W989D6DBGX6E LPSDR memory devices configured for 32b bus. 

The Design passes memory test at FMC_SDCLK@80Mhz.

The Design fails memory test at FMC_SDCLK@100Mhz.

When checking the signal timing, FMC_SDNWE was observed as marginal. 

The design configured I/O High Speed Low voltage and I/O compensation.

Checking the IO types for FMC_SDNWE io pins, the pin options DO NOT indicate the pin is _h type for High speed low voltage. 

What would be the cause of the timing violation?

  

 

 

[KDJEM.1]

Hello @James Panko,

 

Which STM32H750 rev are you using? Is it rev Y or rev V?

Could you please check your PCB? What is the value of capacitance load are you use?

 

Thank you.

Kaouthar

[James Panko]

Hi Kaouthar,

FMC_SDNWE total capacitance: 12pF total (PCB trace - 6pF + SDRAM 1 - 3pF + SDRAM 2 - 3pF) 
FMC_SDCLK total capacitance: 12pF total (PCB trace - 6pF + SDRAM 1 - 3pF + SDRAM 2 - 3pF)

Regards,

Jim

[James Panko]

Hi Kaouthar, STM32H750XBH6TR Rev V Microcontroller, ARM Cortex M7, 400Mhz, 128kB Flash, JPEG, 240+25 TFBGA part is specified.

Regards,

Jim

[KDJEM.1]

Hello @James Panko ,

 

As mentioned in the datasheet, all timing tables are guaranteed for the following FMC_SDCLK maximum values and for capacity load condition:
• For 2.7 V<VDD<3.6 V: FMC_SDCLK =110 MHz at 20 pF
• For 1.8 V<VDD<1.9 V: FMC_SDCLK =100 MHz at 20 pF
• For 1.62 V<DD<1.8 V, FMC_SDCLK =100 MHz at 15 pF

May be this extra delay is due to capacity load.

Thank you.

Kaouthar