STM32H750 LTDC Issues on Intermittent display abnormalities

[martin_xu]

Hello everyone,

      I'm facing an issues with STM32H750 custom Board.

       Configuration:

        1. FMC connect 32MB SDRAM

        2. 32MB QSPI (Code run at QSPI)

        3. 1024x600 16bit TFT-LCD(Framebuffer locate at SDRAM 0xC0000000-0xC012C000)

        4. CubeMX 6.9.0
        5. LVGL 9.0

        For The TFT-LCD Display issues please refer to the link:  

https://www.bilibili.com/video/BV1TK421t7HW/?buvid=YA485EAFDF56A31C481C86916B8359C50235&is_story_h5=false&mid=Zza1nTX4w1vuc1wMnfWTXQ%3D%3D&p=1&plat_id=168&share_from=ugc&share_medium=iphone&share_plat=ios&share_session_id=A10F6F9B-EC8B-4F33-AF59-68892CE424BD&share_source=COPY&share_tag=s_i&spmid=main.my-history-search-result.option-more.0&timestamp=1710145211&unique_k=ieCru03&up_id=650830460

      Similar ltdc signal been interrupted.

     I also have done following test :

     Try to disable _DMA2D_Copy by set the global variable “disable_flush” to 1 in the route disp_flush in the lvgl disp port  file lv_port_disp_template.c  in order to stop any update on ltdc framebuffer.  

   

        But I still see the issues.

        What could be the reason for this?

        Has anyone faced a similar issue or have ideas on how we can resolve these problems?
        Any help or suggestions would be greatly appreciated.
       Thanks in advance!

    

     

 

[KDJEM.1]

Hello @martin_xu ,

Which TFT-LCD reference and LTDC clock are you using?

Please try to reduce the LTDC clock.

I recommend you to take a look at this discussion, I think might be facing the same issue.

Also I advise you to check the AN4861.

I hope this help you.

Kaouthar

[martin_xu]

Hello Kaouthar,

      Thank you very much for your quickly replay.

      For TFT-LCD detail information please check attached TFT_LCD_JLL01ZJGI55-10254Y.pdf. 

      Current the LTDC clock is 55Mhz.

      Reduce the clock to 40 and 30Mhz, it is not effect and still see display flicker.

      I can see LTDC_IER_FUIE Error , After enable the LTDC_ER_IRQHandler while LCD flicker.

      It seem that it is a LTDC bandwidth issues, are there other solution?

      By the way, there are  a very strange phenomenon.

      if I remove a array define "static char dump_buffer[400]={11,12}; "（occupy 400 bytes）,

      it is working fine. 

      Based on this test case, I cannot understand the bandwidth issues. 

     Also, My gui application update lvgl ui object values every 1 second,

     the lvgl draw buffer is locate at ExtSDRAM , it will lead to access to ExtSDRAM.

     Just a other problem, is it possible that set the AHB bus Master Priority(LTDC/Cortex-M7)?

     if so, set the highest Priority for LTDC because another master access request can been delay.

   

     Thanks in advance!

      Martin.xu

 

 

 

       

[KDJEM.1]

Hello @martin_xu ,

I recommend you to check the AN4861 and precisely section 4.2.2 Checking display compatibility considering the memory bandwidth requirements. This section explains how to check a display compatibility considering the framebuffer memory bandwidth. Also can help you to determinate pixel clock and LTDC required bandwidth.

About the priority, setting a higher priority for an ASIB ensures a lower latency for transactions initiated by the associated bus master. This can be useful for real-time-constrained tasks, such as graphics processing (LTDC, DMA2D). Assigning a high priority to masters that can make many and frequent accesses to the same slave (such as the Cortex-M7 CPU) can block access to that slave by other lower-priority masters.

For more information about the priority, I advise you to take a look at RM0433 precisely section 2.2.3 AXI interconnect functional description.

I hope this answer your request!

Thank you.

Kaouthar

 

[martin_xu]

Hello Kaouthar,

       Let me show our hardware config information:

        MCU M7 Clk: 480Mhz

        QSPI: 32MB  run at 4-wire mode(App Fw Code is running at QSPI)

       TFT-LCD: 1024X600  16bit ,LCD_CLK: 55MHZ , LTDC layer = 1       

        SDRAM: 32-bit  32MB 

        System clock HCLK = 240 MHz, SDRAM runs at 80 MHz  (Also test 120MHZ but have no effect)    

       I have double checked the AN4861 and precisely section 4.2.2 Checking display compatibility considering the memory bandwidth requirements. 

               Current the LCD Clk is 55Mhz, So, I think it is ok for  the memory bandwidth requirements.

         Maybe  some unknown reasons have increased the sdram access load,

         Can you take a look my test result?

         Although this is a very puzzling phenomenon，But  I have double checked those testing results.

         it will no filcker, if I just modify the code  about the variable array  printf_str  define way 

        xxx_function()

       {

          static char printf_str[ABNORMAL_STOP_HYDRATE+1][40]          //  The LCD Filcker  

         ....

        }

        xxx_function()

       {

         char printf_str[ABNORMAL_STOP_HYDRATE+1][40]          //  Just remove "static", The LCD no Filcker (workfine) 

         ....

        }

      

       For your reference The attched is the two file.      

            

      Thanks in advance!

      Martin.xu

  

         

[martin_xu]

Hello Kaouthar,

      Regarding this issue, Do you have any other suggestions ? 

  Thanks in advance!

  Martin.xu