STM32H755 dual ADC DMA sample rate is half
Hi,
I'm using STM32H755 nucleo board and evaluating ADC. I'm using ADC1 and ADC2. I like to get 1.92MSPS per ADC (12bit). According to my understanding I need minimum 8 cycles for conversion and therefor I was using 15.36MHz clock rate. With these settings, I'm getting 960kSPS rate, which is half what I expected. Then I doubled clock rate to 30.72MHz, which gives correct 1.92MSPS per ADC. According to AN5354, maximum ADC frequency is 17MHz (LQFP144), which is much lower than my current setting. Can I use 30.72MHz clock for ADC and why it has to be double?
