STM32H755, is the clock too slow?

[halbeeee]

Hello everyone, I'm working on an STM32H755BI (industrial temperature range), and i'm quite disappointed by the maximum clock reachable from the system.

As can be seen, the MCU can reach up to 480MHz in the core M7 and 240MHz in the core M4.

After months of develpment, a firmware package update blocked me the VOS0 and VOS1, and in fact reading the user manual those modes are unavailable on my package, so i reduced to 300MHz and 150MHz

Today, with an update of cube MX, this error appeared in the clock tree:

And in fact by reading the datasheet APB4 is limited to 100MHz.

Reducing APB4 to 100MHZ could not be a big deal, but the real problem is that considering the clock distribution in the previous image the clock of the APB4 is the same clock of the M4 (CPU2).

 

Does this means that i bought a 480+240MHz and i'm forced to use it at 300+100 after more than a year of development?

[mƎALLEm]

Hello,

I didn't read the overall discussion here (3 pages!) but what I wanted to mention is that even with industrial temp range devices (xxx3) you can use VOS0 @480MHz provided that TJmax=105°C for VOS0 and  TJmax=125°C for VOS1 as stated by the note:

May be you need to select the STM32H755xxx6 in CubeMx to workaround this but in final you need to respect the temperature ranges ..

[Tesla DeLorean]

@mƎALLEm @STOne-32 

Is there any preclusion from running AHB4 at DIV1, where the M4 and M7 run at the same speed, synchronously? ie 200/200 MHz or 240/240

Or is it just a lack of creative thinking with regard to the operational frequency of the transistors and temperatures?

Are there critical paths in the M4 design, pipeline, prefetch paths and "caching" specifically exacerbated by temperature, or cause localized heating? Because it strikes me that there should be head-room above 240 MHz in the -40 to 85C, and as you derate the device to get to the broader temperature range are there some opportunities to balance this more effectively. This currently seems competitively crippling, for the sake of making the documentation and testing/characterization simpler.

Don't take this as a criticism, but more of a query of why something is being done or presented in a certain way. Looking for your thoughts and feedback.

Perhaps die level heat maps showing functional units, vs operating speed, or other supporting materials?

[mƎALLEm]

@Tesla DeLorean 

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Is there any preclusion from running AHB4 at DIV1, where the M4 and M7 run at the same speed, synchronously? ie 200/200 MHz or 240/240

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I don't think there is a limitation where the M4 and M7 could run at the same speed.

It could be 240/240MHz or 200/200MHz.

Is there something that indicates this "limitation" in our documentation?