STM32L476RE output characteristic impedance

[LucasRosa]

Hi team,

I am currently developing a board with the STM32L476RET6. This project involves UART communication (UART4, PA0 and PA1), and I am concerned about EMI due to the fast rising and falling edges of the TX signal. To address this issue, I am implementing a series termination. I already have a 50-ohm controlled impedance board. To complete the design, I need to know the output characteristic impedance of the GPIOs I am using. I have tried to find this information in the datasheet and reference manual, but unfortunately, I could not locate it. Can you help me with this?

[LucasRosa]

Hi,

Is this information available? I already found the GPIO capacitance (~5pF). If I also had the inductance, it would be enough to calculate.

[ONadr.1]

I think looking for the impedance of the digital output is pointless. Nothing like that is defined. For the digital output, the maximum output current in the H and L level and the maximum steepness of the edges are defined. In addition, these values ​​may be dependent on the supply voltage.

[LucasRosa]

Hi, thank you for your reply.

ST's L4 series has rising and falling edges of less than 1 ns. The high-performance series clock goes beyond 400 MHz. How should I handle high-speed digital design? Is there no information regarding the characteristic impedance of its GPIOs for EMC? If so, how can I design a high-speed bus? Am I missing something?

[BarryWhit]

 

GPIOs are exactly that - General Purpose. They're not usually fully fully characterized for High-Speed design (unlike transceivers). It's possible that their output impedance is not even consistent enough to specify.  

 

> ST's L4 series has rising and falling edges of less than 1 ns. 

Actually, based on the datasheet's "Output timing characteristic", with the GPIOs at their default speed (set after reset), the rise-time is 17ns-25ns depending on CL and VCC. [UPDATE: this is wrong. the numbers I quoted are the MAX rise-time, which is not helpful]

 

It's an interesting question, whether the "connectivity" (UART,SPI) peripherals make use of the GPIO buffers (*), or if the alternate function actually connects the pin to something else? I don't know the answer to that, but my guess is they just use the GPIO buffers. As @AScha.3  pointed out, those GPIO ports can be configured for different speeds. At reset they are set to the lowest speed. At the highest speed, with a small load, they can reach get down to 1.8ns (which *is* surprisingly fast).

So, just use lower speeds. No one would use a UART for "Ludicrous Speed", and even at the higher end of where you would use a UART, say 8mbps, the clock period is still a comfy 125ns. async UARTs are purpose-built to sample half-way through a clock-period, so the slowest rise-time should be fine for typical loads.  But that's SI, not EMI.

 

> The high-performance series clock goes beyond 400 MHz.

 

But that's irrelevant here. That's the internal clock generated by the PLL which feeds the processor and internal busses,

it does not dictate the rise-time of the output buffers which drive signals off-chip.

 

> I already found the GPIO capacitance (~5pF). If I also had the inductance, it would be enough to calculate.

I'm pretty sure what the data sheet calls "I/O capacitance = 5pf" is actually just input capacitance at the (GP)I/O pin, and this won't help you at all with output impedance (driver output capacitance? I'm not sure that's even a thing in datasheets).

It doesn't even matter for input impedance. Since you're using series-termination (AKA reflected-wave termination), you must be assuming that the input impedance is very high (as well you should, the input is most likely the gate of a FET)

 

It wouldn't hurt to do is a simulation with the IBIS files ST provides. For one thing, they can help you decide on the size of your series termination, if you think you need one.

 

Since you specifically mention EMI ( rather than SI concerns),  can you tell us more about the requirements you're designing for? is your board going to be tested for regulatory EMC compliance? are you sure what you're worried about is even an issue?

 

(*) Late Update: 

My question is answered in 

http://efton.sk/STM32/gotcha/g14.html

 

"the same set of transistors drives the output when set to GPIO Out and when set to Alternate Function (in GPIOx_MODER), if some peripheral is set to output a waveform of given frequency (e.g. Timer outputting PWM), this parameter ensures that with appropriate setting of GPIOx_OSPEEDR the given frequency is attainable."

 

So, the GPIO speed settings do also control the edge rate of the SPI, as I guessed.

 

[BarryWhit]

---

@BarryWhit wrote:

 

(driver output capacitance? I'm not sure that's even a thing in datasheets). 

---

well-waddayaknow....

This is for a buffer from TI. They don't show the test circuit, so not sure what this actually is.

[BarryWhit]

 

 

Thanks for the Accept, but my analysis is actually wrong. I just noticed I was looking at the Max. rise time, which isn't what we care about at all. I can still say that an IBIS simulation would tell you more, and would definitely help you choose the series-termination resistor to use.  

 

Update: perhaps there *is* something we can derive indirectly about the rise-time simply from the datasheet tables alone. ST also specifies Max frequency for each GPIO speed setting, depending on CL and VCC. This doesn't explicitly tell you what the rise-time is, but we can assume that a modest upper bound on frequency for Low-speed (00) means the rise-time is also nothing too shocking. WIth the default Low-speed(00), for 3.3V and CL=10PF (the fastest case), the datasheet gives 10Mhz as the maximum frequency. That's  somewhat higher than the top rate you would normally run a UART at, but still in the ballpark, and suggests a rise-time on the order of 10ns (depending on which rule-of-thumb you use).

 

I don't think you should worry too much about EMI generated from this particular source.

 

 

[BarryWhit]

I had not personally done this before, but it turns out you can manually calculate a good approximation to the buffer output impedance from the IBIS file. See Driver’s Output Impedance From IBIS - Bert Simonovich Blog.

Once someone explains it, it seems very obvious how to do it ;) .

 

Basically, IBIS models contain transition waveforms for low-to-high and high-to-low transition with a known resistive load. Based on settled voltage after a low-to-high transition, you can easily calculate the output impedance since it's  a simple voltage divider circuit. Simonovich has more information, and it's worth reading the rest of his papers and blogs if you care about SI topics.

[LucasRosa]

Hi,

Thank you for the warning. Additionally, I was searching for more information about it and found a video that explains series termination quite well. Coincidentally, it cites the same reference you have attached.

Here is the video: https://www.youtube.com/watch?v=nYvZ791-VZM