STM32L4xx TAMP/BKP register use problems

[mwp]

Greetings,

I'm attempting to make use of the tamper backup registers.

I am enabling the RTC and have using LSI as the clock source.
ROP is not enabled, I am not using the TAMP input pins, and i am debugging via SWD.

As it is at the moment, writing a value using LL_RTC_BKP_SetRegister() then immediately reading back the value using LL_RTC_BKP_GetRegister() always returns a value of 0.

I've read through the reference manual. There does not appear to be mentioned any other peripherals/clocks/flags that need to be enabled before using the backup regs. Is that correct?

Thanks in advance!

 

[Pierre_Paris]

Hello @mwp,

Here are some indications :

• There are 32 RTC backup registers (RTC_BKPxR) . They are powered-on by VBAT when VDD is swhitched off. Are you turning off the power supply ? What is your VBAT value ? Are you performing a System Reset ?
• What is your read protection (RDP) level ? 
• How are you calling both functions ? Can you share ?

Best Regards,

Pierre

[JPeac.1]

Is access to the backp domain enabled?   PWR->CR1 |= PWR_CR1_DBP;

 

[mwp]

Thanks for the questions.

I'm simply writing to a backup register, and reading it shortly afterward. I'm not changing power mode, etc.
RDP is not enabled (level 0).

 

 

LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_RTCAPB); // not sure if this is needed?
LL_RCC_SetRTCClockSource(LL_RCC_RTC_CLKSOURCE_LSI);
LL_RCC_EnableRTC();
LL_PWR_EnableBkUpAccess();
//a number to store
uint32_t WriteRand = 0x12345678;
//keep in the backup domain reg
LL_RTC_BKP_SetRegister(TAMP, LL_RTC_BKP_DR9, WriteRand);
//something
HAL_Delay(10);
//read back to make sure it worked
uint32_t ReadRand;
ReadRand = LL_RTC_BKP_GetRegister(TAMP, LL_RTC_BKP_DR9);

 

 

 

That's a stripped down example of what i'm doing.

WriteRand and ReadRand are not the same. ReadRand is always 0.

[waclawek.jan]

Which 'L4?

What hardware ("known good" like Nucleo, or your own)? And the same question as Pierre asked above: how is VBAT connected?

Do you intend to use RTC? Can you read out RTC registers content?

JW

[Pierre_Paris]

All right, Have you followed these steps to enable access to the backup domain ?
1. Enable the power interface clock by setting the PWREN bits in the Section 6.4.19:
APB1 peripheral clock enable register 1 (RCC_APB1ENR1)
2. Set the DBP bit in the Power control register 1 (PWR_CR1) to enable access to the
backup domain
3. Select the RTC clock source in the Backup domain control register (RCC_BDCR).
4. Enable the RTC clock by setting the RTCEN [15] bit in the Backup domain control
register (RCC_BDCR).

Best Regards,

Pierre

[waclawek.jan]

@Pierre_Paris,

Is RTC clock needed to use the backup registers?

JW

[mwp]

My application is using a L412KB, and the Nucleo im testing with at the moment is a genuine L412KB Nucleo.

The L412KB package has VBAT internally connected to VDD.

I do intend to use RTC for periodic wakeup from standby mode (this isn't enabled at the moment).

[mwp]

I just found the problem...

RTC reg write protection needed to be disabled.

 

 

>> LL_RTC_DisableWriteProtection(RTC);

 

Thanks everyone for the help!

[waclawek.jan]

@mwp,

Thanks for coming back with the solution.

@Pierre_Paris,

In contrast to all other 'L4, 'L412 has RTCv3 with separate TAMP, and the backup registers are part of TAMP. Can you please have a look at these problems:

- in RM0394rev4, in STM32L41xxx/42xxx/43xxx/44xxx/45xxx/46xxx memory map and peripheral register
boundary addresses table, TAMP is missing, so we don't know what's its address.

- TAMP address definition in the CMSIS-mandated device header is suffixed U, whereas all other peripherals' addresses definitions are suffixed UL. What's the reason for the difference?

- in RM, TAMP chapter should say it's 'L41x/'L42x specific

- there's no mention of the need for performing the RTC-write-protection-removal in order to access the backup registers or any other TAMP registers. The RTC register write protection subchapter in the RTCv3 chapter lists the protected registers, so protected TAMP registers ought to be mentioned there, too. And, of course, this has to be added to the TAMP chapter, too.

- TAMP chapter says, "The TAMP kernel clock is usually the LSE at 32.768 kHz although it is possible to select
other clock sources in the RCC (refer to RCC for more details)." However, there's no TAMP mention in the RCC chapter.

- please clarify your remark above on need for RTC clock for backup registers to be accessed, both in RTCv2 and RTCv3 context.

Thanks,

JW